On Fri, 2017-01-13 at 18:05 +0530, Vinod Koul wrote:
>
> > +static void idma32_fifo_partition(struct dw_dma *dw)
> > +{
> > + u64 value = IDMA32C_FP_PSIZE_CH0(128) |
> > IDMA32C_FP_PSIZE_CH1(128) |
> > + IDMA32C_FP_UPDATE;
> > + u64 fifo_partition = 0;
> > +
> > + if (!dw->pdata->is_idma32)
> > + return;
> > +
> > + /* Fill FIFO_PARTITION low bits (Channels 0..1, 4..5) */
> > + fifo_partition |= value << 0;
> > +
> > + /* Fill FIFO_PARTITION high bits (Channels 2..3, 6..7) */
> > + fifo_partition |= value << 32;
> > +
> > + /* Program FIFO Partition registers - 128 bytes for each
> > channel */
> > + idma32_writeq(dw, FIFO_PARTITION1, fifo_partition);
> > + idma32_writeq(dw, FIFO_PARTITION0, fifo_partition);
> > +}
>
> Don't recall what was this about, care to detail this one..
By default full FIFO (1024 bytes) is assigned to channel 0.
By programming these registers we setup equal parts of FIFO. More
detailed it's described in SC DMA HAS, IIRC.
Should I put this to commit message or as comment to the function?
--
Andy Shevchenko <andriy.shevchenko@xxxxxxxxxxxxxxx>
Intel Finland Oy
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