On 08/12/2016 13:44, Måns Rullgård wrote: > Mason <slash.tmp@xxxxxxx> writes: > >> On 08/12/2016 13:20, Måns Rullgård wrote: >> >>> The only problem we have is that nobody envisioned hardware where the >>> dma engine indicates completion slightly too soon. I suspect there's a >>> fifo or such somewhere, and the interrupt is triggered when the last >>> byte has been placed in the fifo rather than when it has been removed >>> which would have been more correct. >> >> As I (tried to) explain here: >> https://marc.info/?l=dmaengine&m=148007808418242&w=2 >> >> A *read* MBUS agent raises its IRQ when it is safe for the memory >> to be overwritten (i.e. every byte has been pushed into the pipe). >> >> A *write* MBUS agent raises its IRQ when it is safe for another >> agent to read any one of the transferred bytes. >> >> The issue comes from the fact that, for a memory-to-device transfer, >> the system will receive the read agent's IRQ, but most devices >> (NFC, SATA) don't have an IRQ line to signal that their part of the >> operation is complete. > > SATA does, actually. Nevertheless, it's an unusual design. Thanks, I was mistaken about the SATA controller. On tango3 (and also tango4, I assume) IRQ 41 = Serial ATA #0 IRQ 42 = Serial ATA DMA #0 IRQ 54 = Serial ATA #1 IRQ 55 = Serial ATA DMA #1 But in the end, whether there is a device interrupt (SATA) or not (NFC), for a memory-to-device transfer, the DMA driver will get the read agent notification (which should be ignored) and the client driver should either spin until idle (NFC) or wait for its completion IRQ (SATA). Correct? Regards. -- To unsubscribe from this list: send the line "unsubscribe dmaengine" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
