Mason <slash.tmp@xxxxxxx> writes: > On 08/12/2016 13:20, Måns Rullgård wrote: > >> The only problem we have is that nobody envisioned hardware where the >> dma engine indicates completion slightly too soon. I suspect there's a >> fifo or such somewhere, and the interrupt is triggered when the last >> byte has been placed in the fifo rather than when it has been removed >> which would have been more correct. > > As I (tried to) explain here: > https://marc.info/?l=dmaengine&m=148007808418242&w=2 > > A *read* MBUS agent raises its IRQ when it is safe for the memory > to be overwritten (i.e. every byte has been pushed into the pipe). > > A *write* MBUS agent raises its IRQ when it is safe for another > agent to read any one of the transferred bytes. > > The issue comes from the fact that, for a memory-to-device transfer, > the system will receive the read agent's IRQ, but most devices > (NFC, SATA) don't have an IRQ line to signal that their part of the > operation is complete. SATA does, actually. Nevertheless, it's an unusual design. -- Måns Rullgård -- To unsubscribe from this list: send the line "unsubscribe dmaengine" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
