On 26.10.2016 11:30, Andy Shevchenko wrote:
<snip>
But perhaps the DMA controller implementation on BayTrail does not
support to access data on external (non-BayTrail) PCI devices
(data path missing?).
That's correct. It can't perform IO to the devices which are
external.
But we are talking about memory-to-memory accesses, right?
We seem to have a different understanding of "memory-to-memory".
For you this only refers to system memory, right? For me, this
also includes memories such as this FPGA DDR located on the
PCI bus (accessible in the same way as system memory as mentioned
above).
Yes.
But again, the main culprit might be, that the DMA controllers
on BayTrail just have no data patch to access such external PCI
devices.
That's possible. I'm not so familiar with actual interconnect in
BayTrail, but what I know that it's sitting on AHB bus which is bridged
to internal fabric (IOSF). All request lines of both DMA controllers are
wired to internal (LPSS) devices.
AFAICT, we don't need any request lines for my type of "memory-to-
memory" transfers. Such request lines should only be needed for
"synchronous device transfers", where the device requests new data
(e.g. FIFO empty or ready...). Or am I missing something here?
Could you perhaps ask a bit around about this potential limitation?
This is very important to us and any information about this would
be very helpful and really appreciated.
Thanks,
Stefan
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