RE: DMA Engine API multiplanar support

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Ping!

> -----Original Message-----
> From: Radhey Shyam Pandey
> Sent: Wednesday, July 13, 2016 4:55 PM
> To: 'dmaengine@xxxxxxxxxxxxxxx' <dmaengine@xxxxxxxxxxxxxxx>
> Cc: Hyun Kwon <hyunk@xxxxxxxxxx>; Kedareswara rao Appana
> (appana.durga.rao@xxxxxxxxxx) <appana.durga.rao@xxxxxxxxxx>; Laurent
> Pinchart (laurent.pinchart@xxxxxxxxxxxxxxxx)
> <laurent.pinchart@xxxxxxxxxxxxxxxx>; nofooter <nofooter@xxxxxxxxxx>
> Subject: DMA Engine API multiplanar support
>
> Hello All,
>
> I am planning to write DMA driver for new Xilinx VDMA IP (HLS Based) and
> integrate it with Xilinx V4L2 capture pipeline.
>
> For single DMA read/write transaction hardware requires two physically
> separate buffers for Y and CbCr components, which must be placed in two
> different memory banks.
> i.e DMA reads YUV AXI-Stream for source(DEV) and put it MEM into planar
> format.
>
>
> V4L2_PIX_FMT_NV16 (Description)
> These are two-plane versions of the YUV 4:2:2 format.
> The three components are separated into two sub-images or planes.
> The Y plane is first. The Y plane has one byte per pixel.
> For V4L2_PIX_FMT_NV16, a combined CbCr plane immediately follows the Y
> plane in memory.
> The CbCr plane is the same width and height, in bytes, as the Y plane (and of
> the image).
>
> So I need some attribute in struct dma_channel to indicate that it supports
> packed/planar format?
>
> Also while programming DMA we need to provide the base address of Y
> plane and UV plane to hardware for one DMA transaction.
> Current dmaengine_prep_* implementations doesn't provide an interface to
> program multiplanar channel address.
>
> One way is to split programming of DMA channel into two
> dma_async_tx_descriptor's for each channel (Y and UV) request but that
> doesn't looks right. There will be two DMA/callbacks programming for a
> single DMA write/read transaction.
> Any suggestions?
>
> Thanks,
> Radhey


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