Hi Laurent Pinchart, > -----Original Message----- > From: Laurent Pinchart [mailto:laurent.pinchart@xxxxxxxxxxxxxxxx] > Sent: Monday, March 21, 2016 9:48 PM > To: Anurag Kumar Vulisha > Cc: Vinod Koul; Rob Herring; Pawel Moll; Mark Rutland; Ian Campbell; Kumar > Gala; Michal Simek; Soren Brinkmann; Dan Williams; afaerber@xxxxxxx; Maxime > Ripard; Appana Durga Kedareswara Rao; Anirudha Sarangi; Srikanth Vemula; > devicetree@xxxxxxxxxxxxxxx; linux-arm-kernel@xxxxxxxxxxxxxxxxxxx; linux- > kernel@xxxxxxxxxxxxxxx; dmaengine@xxxxxxxxxxxxxxx > Subject: Re: [PATCH v2] dmaengine: vdma: Add 64 bit addressing support to the > driver > > Hi Anurag, > > On Wednesday 23 Sep 2015 15:12:36 Anurag Kumar Vulisha wrote: > > On Monday, September 21, 2015 9:27 PM Vinod Koul wrote: > > > On Thu, Aug 27, 2015 at 09:19:18PM +0530, Anurag Kumar Vulisha wrote: > > >> This VDMA is a soft ip, which can be programmed to support > > >> 32 bit addressing or greater than 32 bit addressing. > > >> > > >> When the VDMA ip is configured for 32 bit address space the > > >> transfer start address is specified by a single register. > > > > > > would be good to specfiy which one > > > > Will change this in v3 > > What happened to v3 ? :-) I have sent it today. Thanks, Kedar. > > > >> When the VDMA core is configured for an address space greater than > > >> 32 then each start address is specified by a combination of two > > >> registers. The first register specifies the LSB 32 bits of address, > > >> while the next register specifies the MSB 32 bits of address.For > > >> example,5Ch will specify the LSB 32 bits while 60h will specify the > > >> MSB 32 bits of the first start address.So we need to program two > > >> registers at a time. > > > > > > can we have spaces after full stops and commas! > > > > Will take care of this in v3 patch. > > > > >> +/* Since vdma driver is trying to write to a register offset which > > >> +is not a > > >> + * multiple of 64 bits(ex : 0x5c), we are writing as two separate > > >> +32 bits > > >> + * instead of a single 64 bit register write. > > >> + */ > > > > > > This is not kernel style for multi-lines, pls refer to > > > Documentation/CodingStyle > > > > Will address this in v3 patch > > > > >> + > > >> +static inline void vdma_desc_write_64(struct xilinx_vdma_chan > > >> +*chan, > > >> u32 reg, > > >> + u32 value_lsb, u32 value_msb) { > > >> + /* Write the lsb 32 bits*/ > > >> + writel(value_lsb, chan->xdev->regs + chan->desc_offset + reg); > > >> + > > >> + /* Write the msb 32 bits */ > > >> + writel(value_msb, chan->xdev->regs + chan->desc_offset + reg + > > >> + 4); > > > > > > why not writeq > > > > We are trying to write at a register address(ex:0x5c) which is not > > aligned on 8 bytes boundary.So if I try to use 64 bit write on > > it,unalignment fault is getting generated.To avoid that we are using > > two separate 32 bit writes. We had this discussion in previous > > versions of this patch with Laurent Pinchart .I have also added this > > exaplanation in the comments above this function. > > > > >> + err = of_property_read_u32(node, "xlnx,addrwidth", > > >> + &addr_width); > > >> + > > >> + if (err < 0) { > > >> + /* Setting addr_width property to default 32 bits */ > > >> + addr_width = 32; > > >> + } > > > > > > braces for a single line statement! Also space is redandant before > > > if condition > > > > Will take care of this in v3 patch > > -- > Regards, > > Laurent Pinchart -- To unsubscribe from this list: send the line "unsubscribe dmaengine" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
