Re: [PATCH 1/2] dmaengine: zxdma: Fix data width bug

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2015-08-05 11:38 GMT+08:00 Vinod Koul <vinod.koul@xxxxxxxxx>:
> On Wed, Aug 05, 2015 at 11:32:00AM +0800, Jun Nie wrote:
>> 2015-08-05 11:24 GMT+08:00 Vinod Koul <vinod.koul@xxxxxxxxx>:
>> > On Tue, Jul 21, 2015 at 11:01:05AM +0800, Jun Nie wrote:
>> >> Align src and dst width to fix data alignment issue. Hardware
>> >> burst length limitation can be addressed well too.
>> > What is the data alignment issue you have? Why not document that in code and
>> > changelog?
>
> ??
>
When buffer size is not multiple of burst length * data width, src/dst
data width should be identical for these residue data. Will doc it in
commit log and code in next version patch.
>
>> >>
>> >> Signed-off-by: Jun Nie <jun.nie@xxxxxxxxxx>
>> >> ---
>> >>  drivers/dma/zx296702_dma.c | 8 ++++----
>> >>  1 file changed, 4 insertions(+), 4 deletions(-)
>> >>
>> >> diff --git a/drivers/dma/zx296702_dma.c b/drivers/dma/zx296702_dma.c
>> >> index ec470bc..4757f74 100644
>> >> --- a/drivers/dma/zx296702_dma.c
>> >> +++ b/drivers/dma/zx296702_dma.c
>> >> @@ -143,6 +143,7 @@ static void zx_dma_terminate_chan(struct zx_dma_phy *phy, struct zx_dma_dev *d)
>> >>
>> >>       val = readl_relaxed(phy->base + REG_ZX_CTRL);
>> >>       val &= ~ZX_CH_ENABLE;
>> >> +     val |= ZX_FORCE_CLOSE;
>> > how is this related to data width?
>>
>> Burst length has limitation and destination burst length is calculated
>> from other src/dst parameters. So it is safe to align src/dst data
>> width to avoid to run into limitation.
>
> thats fine but what does it have to do with terminate and ZX_FORCE_CLOSE?

It fix other bug that's really do not relate to data width. Hardware
will not stop till all transmit ion is done when enable bit is
cleared. Cyclic DMA does not stop without the change as a result of
ring DMA chain. Seems it should be changed in cyclic dma patch. A new
patch should be prepare now, right?

Jun
>
> --
> ~Vinod
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