On Wed, Apr 29, 2015 at 09:49:05PM +0800, Jun Nie wrote:
> +#define DRIVER_NAME "zx-dma"
> +#define DMA_ALIGN 4
> +#define DMA_MAX_SIZE (0x10000 - PAGE_SIZE)
> +#define LLI_BLOCK_SIZE (4 * PAGE_SIZE)
> +
> +#define REG_SRC_ADDR 0x00
> +#define REG_DST_ADDR 0x04
> +#define REG_TX_X_COUNT 0x08
> +#define REG_TX_ZY_COUNT 0x0c
> +#define REG_SRC_ZY_STEP 0x10
> +#define REG_DST_ZY_STEP 0x14
> +#define REG_LLI_ADDR 0x1c
> +#define REG_CTRL 0x20
> +#define REG_TC_IRQ 0x800
> +#define REG_SRC_ERR_IRQ 0x804
> +#define REG_DST_ERR_IRQ 0x808
> +#define REG_CFG_ERR_IRQ 0x80c
> +#define REG_TC_IRQ_RAW 0x810
> +#define REG_SRC_ERR_IRQ_RAW 0x814
> +#define REG_DST_ERR_IRQ_RAW 0x818
> +#define REG_CFG_ERR_IRQ_RAW 0x81c
> +#define REG_STATUS 0x820
> +#define REG_DMA_GRP_PRIO 0x824
> +#define REG_DMA_ARB 0x828
these should be namespaced..
> +
> +#define FORCE_CLOSE BIT(31)
> +#define DST_BURST_WIDTH(x) (((x) & 0x7) << 13)
> +#define MAX_BURST_LEN 16
> +#define SRC_BURST_LEN(x) (((x) & 0xf) << 9)
> +#define SRC_BURST_WIDTH(x) (((x) & 0x7) << 6)
> +#define IRQ_ENABLE_TC BIT(4)
> +#define IRQ_ENABLE_ERR BIT(5)
> +#define IRQ_ENABLE_ALL (3 << 4)
> +#define DST_FIFO_MODE BIT(3)
> +#define SRC_FIFO_MODE BIT(2)
> +#define SOFT_REQ BIT(1)
> +#define CH_ENABLE BIT(0)
ditto
> +struct zx_desc_hw {
> + u32 saddr;
> + u32 daddr;
> + u32 src_x;
> + u32 src_zy;
> + u32 src_zy_step;
> + u32 dst_zy_step;
> + u32 reserved1;
> + u32 lli;
> + u32 ctr;
> + u32 reserved[7]; /* pack as 64B */
> +} __aligned(32);
why 7 then, one u32 should have aligned...
> +static enum dma_status zx_dma_tx_status(struct dma_chan *chan,
> + dma_cookie_t cookie,
> + struct dma_tx_state *state)
> +{
> + struct zx_dma_chan *c = to_zx_chan(chan);
> + struct zx_dma_phy *p;
> + struct virt_dma_desc *vd;
> + unsigned long flags;
> + enum dma_status ret;
> + size_t bytes = 0;
> +
> + ret = dma_cookie_status(&c->vc.chan, cookie, state);
> + if (ret == DMA_COMPLETE)
or !state, it can be null, so no need for computation then
> +static enum zx_dma_burst_width zx_dma_burst_width(enum dma_slave_buswidth width)
> +{
> + switch (width) {
> + case DMA_SLAVE_BUSWIDTH_1_BYTE:
> + return ZX_DMA_WIDTH_8BIT;
> + case DMA_SLAVE_BUSWIDTH_2_BYTES:
> + return ZX_DMA_WIDTH_16BIT;
> + case DMA_SLAVE_BUSWIDTH_4_BYTES:
> + return ZX_DMA_WIDTH_32BIT;
> + case DMA_SLAVE_BUSWIDTH_8_BYTES:
> + return ZX_DMA_WIDTH_64BIT;
sounds like ffs(width) - 1...
> + default:
> + return ZX_DMA_WIDTH_32BIT;
> + }
> +}
> +
> +static int zx_dma_config(struct dma_chan *chan,
> + struct dma_slave_config *cfg)
> +{
> + struct zx_dma_chan *c = to_zx_chan(chan);
> + struct zx_dma_dev *d = to_zx_dma(chan->device);
> + enum zx_dma_burst_width src_width;
> + enum zx_dma_burst_width dst_width;
> + u32 maxburst = 0;
> +
> + if (!cfg)
> + return -EINVAL;
> +
> + c->dir = cfg->direction;
direction is depricated pls dont use that. You need to copy slave config
here and use in prep functions. Direction is an argument in prep_ calls
> +
> +static const struct of_device_id zx6702_dma_dt_ids[] = {
> + { .compatible = "zte,zx296702-dma", },
where are the bindings?
--
~Vinod
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