Re: [PATCH] dmaengine: dw: disable BLOCK interrupts in dw_dma_off()

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On Tue, 2015-01-20 at 14:41 +0800, Keyon wrote:
> hi, Andy,
> 
> will this change disable dw_dma_interrupt when dw_dma is set to off?
> 
> I am debugging an ADSP issue on BDW and thinking of that we need disable 
> this interrupt(at least disable the interrupt reset part) when no 
> channel is used(dw->in_use == 0).

This driver is not using it at all, so, this patch is a rather cosmetic
change. Do you have this interrupt enabled by some reason (firmware?)?

If so, then it might make sense to disable it at interrupt handler as
well.

> 
> ~Keyon
> 
> On 2015年01月20日 00:20, Andy Shevchenko wrote:
> > This patch moves disabling BLOCK interrupts code to dw_dma_off() function. It
> > makes code a bit more consistent.
> >
> > Signed-off-by: Andy Shevchenko <andriy.shevchenko@xxxxxxxxxxxxxxx>
> > ---
> >   drivers/dma/dw/core.c | 4 +---
> >   1 file changed, 1 insertion(+), 3 deletions(-)
> >
> > diff --git a/drivers/dma/dw/core.c b/drivers/dma/dw/core.c
> > index 0e7d94e..551edc3 100644
> > --- a/drivers/dma/dw/core.c
> > +++ b/drivers/dma/dw/core.c
> > @@ -1118,6 +1118,7 @@ static void dw_dma_off(struct dw_dma *dw)
> >   	dma_writel(dw, CFG, 0);
> >   
> >   	channel_clear_bit(dw, MASK.XFER, dw->all_chan_mask);
> > +	channel_clear_bit(dw, MASK.BLOCK, dw->all_chan_mask);
> >   	channel_clear_bit(dw, MASK.SRC_TRAN, dw->all_chan_mask);
> >   	channel_clear_bit(dw, MASK.DST_TRAN, dw->all_chan_mask);
> >   	channel_clear_bit(dw, MASK.ERROR, dw->all_chan_mask);
> > @@ -1574,9 +1575,6 @@ int dw_dma_probe(struct dw_dma_chip *chip, struct dw_dma_platform_data *pdata)
> >   	/* Force dma off, just in case */
> >   	dw_dma_off(dw);
> >   
> > -	/* Disable BLOCK interrupts as well */
> > -	channel_clear_bit(dw, MASK.BLOCK, dw->all_chan_mask);
> > -
> >   	/* Create a pool of consistent memory blocks for hardware descriptors */
> >   	dw->desc_pool = dmam_pool_create("dw_dmac_desc_pool", chip->dev,
> >   					 sizeof(struct dw_desc), 4, 0);
> 


-- 
Andy Shevchenko <andriy.shevchenko@xxxxxxxxx>
Intel Finland Oy

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