On Thu, 2014-05-08 at 12:01 +0300, Andy Shevchenko wrote:
> hclk signal is a bus clock. So, it means we have to have it enabled during
> access to the DMA controller. This patch makes sure that we enable clock before
> access to the device, though it currently works on Intel hardware.
Vinod, ping?
Could we get this series to v3.16 queue?
>
> Signed-off-by: Andy Shevchenko <andriy.shevchenko@xxxxxxxxxxxxxxx>
> ---
> drivers/dma/dw/core.c | 10 +++++-----
> 1 file changed, 5 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/dma/dw/core.c b/drivers/dma/dw/core.c
> index 7a74076..009dc62 100644
> --- a/drivers/dma/dw/core.c
> +++ b/drivers/dma/dw/core.c
> @@ -1493,6 +1493,11 @@ int dw_dma_probe(struct dw_dma_chip *chip, struct dw_dma_platform_data *pdata)
> dw->regs = chip->regs;
> chip->dw = dw;
>
> + dw->clk = devm_clk_get(chip->dev, "hclk");
> + if (IS_ERR(dw->clk))
> + return PTR_ERR(dw->clk);
> + clk_prepare_enable(dw->clk);
> +
> dw_params = dma_read_byaddr(chip->regs, DW_PARAMS);
> autocfg = dw_params >> DW_PARAMS_EN & 0x1;
>
> @@ -1520,11 +1525,6 @@ int dw_dma_probe(struct dw_dma_chip *chip, struct dw_dma_platform_data *pdata)
> if (!dw->chan)
> return -ENOMEM;
>
> - dw->clk = devm_clk_get(chip->dev, "hclk");
> - if (IS_ERR(dw->clk))
> - return PTR_ERR(dw->clk);
> - clk_prepare_enable(dw->clk);
> -
> /* Get hardware configuration parameters */
> if (autocfg) {
> max_blk_size = dma_readl(dw, MAX_BLK_SIZE);
--
Andy Shevchenko <andriy.shevchenko@xxxxxxxxx>
Intel Finland Oy
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