On 04/11/2014 02:31 PM, Vinod Koul wrote: >> I would say that it is channel based config. I don't see the reason why would >> one mix different priorities on a configured channel between descriptors. >> >>> If not then we can add this in dma_slave_config ? >> >> So adding to the struct for example: >> bool high_priority; > > In designware controller, we can have channel priorties from 0 to 7 which IIRC 7 > being highest. So bool wont work. unsigned int/u8 would be good. I see. But from a generic code what number should one pass if we want to get the highest priority? With eDMA3 we essentially have three levels (see later) so if we receive 7 as priority what shall we do? Just treat as highest? But if we receive 4, which is somewhere in the middle for designware it is still means highest for us. I see this too small step partitioning in common code a bit problematic when it comes to how to interpret the 'magic numbers'. Also how all the driver in the system will decide the priority number? I'm sure they will pick something conveniently average for themselves and I imagine audio would try to pick something which is bigger than the numbers others have taken... > How about your controller, is it binary? We also have priority from 0 to 7, 0 being the highest priority. We have 3 Transfer Controllers/Event Queues and we can set the priority for the TC/EQ and assign the given channel to the desired TC/EQ. So in reality we have 3 priorities to choose from in my view since we only have 3 TC/EQ in eDMA3 (of AM335x/AM447x) on other SoCs we can have different number of TC/EQ. -- Péter -- To unsubscribe from this list: send the line "unsubscribe dmaengine" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
