On Wed, Oct 21, 2015 at 06:20:27PM +0200, Jens Kuske wrote: > + bus_gates: clk@01c20060 { > + #clock-cells = <1>; > + compatible = "allwinner,sun8i-h3-bus-gates-clk"; > + reg = <0x01c20060 0x14>; > + clock-indices = <5>, <6>, <8>, > + <9>, <10>, <13>, > + <14>, <17>, <18>, > + <19>, <20>, > + <21>, <23>, > + <24>, <25>, > + <26>, <27>, > + <28>, <29>, > + <30>, <31>, <32>, > + <35>, <36>, <37>, > + <40>, <41>, <43>, > + <44>, <52>, <53>, > + <54>, <64>, > + <65>, <69>, <72>, > + <76>, <77>, <78>, > + <96>, <97>, <98>, > + <112>, <113>, > + <114>, <115>, <116>, > + <128>, <135>; > + clocks = <&ahb1>, <&ahb1>, <&ahb1>, > + <&ahb1>, <&ahb1>, <&ahb1>, > + <&ahb1>, <&ahb2>, <&ahb1>, > + <&ahb1>, <&ahb1>, > + <&ahb1>, <&ahb1>, > + <&ahb1>, <&ahb1>, > + <&ahb1>, <&ahb1>, > + <&ahb1>, <&ahb2>, > + <&ahb2>, <&ahb2>, <&ahb1>, > + <&ahb1>, <&ahb1>, <&ahb1>, > + <&ahb1>, <&ahb1>, <&ahb1>, > + <&ahb1>, <&ahb1>, <&ahb1>, > + <&ahb1>, <&apb1>, > + <&apb1>, <&apb1>, <&apb1>, > + <&apb1>, <&apb1>, <&apb1>, > + <&apb2>, <&apb2>, <&apb2>, > + <&apb2>, <&apb2>, > + <&apb2>, <&apb2>, <&apb2>, > + <&ahb1>, <&ahb1>; This is not really what I had in mind... This IP has 2 parents, and only two parents. The mapping between the IPs should be done in the driver itself, not in the DT where it is very error prone and barely readable. And note that I never have expected you to use clk-simple-gates either. This is a complicated clock, unlike the other we've seen so far, it definitely deserves a driver of its own. Thanks! Maxime -- Maxime Ripard, Free Electrons Embedded Linux, Kernel and Android engineering http://free-electrons.com
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