2015-10-22 18:44 GMT-07:00 Jaedon Shin <jaedon.shin@xxxxxxxxx>:
> Add offsets for 40nm BMIPS based set-top box platforms.
>
> Signed-off-by: Jaedon Shin <jaedon.shin@xxxxxxxxx>
> ---
> drivers/ata/ahci_brcmstb.c | 11 +++++++++--
> 1 file changed, 9 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/ata/ahci_brcmstb.c b/drivers/ata/ahci_brcmstb.c
> index 8cf6f7d4798f..59eb526cf4f6 100644
> --- a/drivers/ata/ahci_brcmstb.c
> +++ b/drivers/ata/ahci_brcmstb.c
> @@ -50,7 +50,8 @@
> #define SATA_TOP_CTRL_2_SW_RST_RX BIT(2)
> #define SATA_TOP_CTRL_2_SW_RST_TX BIT(3)
> #define SATA_TOP_CTRL_2_PHY_GLOBAL_RESET BIT(14)
> - #define SATA_TOP_CTRL_PHY_OFFS 0x8
> + #define SATA_TOP_CTRL_28NM_PHY_OFFS 0x8
> + #define SATA_TOP_CTRL_40NM_PHY_OFFS 0x4
> #define SATA_TOP_MAX_PHYS 2
> #define SATA_TOP_CTRL_SATA_TP_OUT 0x1c
> #define SATA_TOP_CTRL_CLIENT_INIT_CTRL 0x20
> @@ -237,7 +238,13 @@ static int brcm_ahci_resume(struct device *dev)
>
> static const struct of_device_id ahci_of_match[] = {
> {.compatible = "brcm,bcm7445-ahci",
> - .data = (void *)SATA_TOP_CTRL_PHY_OFFS},
> + .data = (void *)SATA_TOP_CTRL_28NM_PHY_OFFS},
> + {.compatible = "brcm,bcm7346-ahci",
> + .data = (void *)SATA_TOP_CTRL_40NM_PHY_OFFS},
> + {.compatible = "brcm,bcm7360-ahci",
> + .data = (void *)SATA_TOP_CTRL_40NM_PHY_OFFS},
> + {.compatible = "brcm,bcm7362-ahci",
> + .data = (void *)SATA_TOP_CTRL_40NM_PHY_OFFS},
Since you are introducing new compatible strings, you also need to
update the binding document in Documentation/devicetree/bindings/ata/
We could just use the compatible string for the first 40nm chip that
started featuring such a SATA3 AHCI compliant core, which seems to be
7231. Apart from the existing known workarounds (disabling NCQ, tuning
the PHY) it seems to be largely identical across all 40nm chips.
This is fine either way, and more information cannot hurt, these are
all production chips, so we can actually look back at the history to
know everything about them.
--
Florian
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