On Thu, Oct 22, 2015 at 10:29:59AM +0200, Jean-Francois Moine wrote: > On Thu, 22 Oct 2015 10:05:08 +0200 > Maxime Ripard <maxime.ripard@xxxxxxxxxxxxxxxxxx> wrote: > > > > + uart0: serial@01c28000 { > > > + compatible = "snps,dw-apb-uart"; > > > + reg = <0x01c28000 0x400>; > > > + interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; > > > + reg-shift = <2>; > > > + reg-io-width = <4>; > > > + clocks = <&bus_gates 112>; > > > + resets = <&bus_rst 208>; > > > > It's a bit weird that the clocks and reset indices don't match, > > usually they do. > > > > What's even weirder is that there's a 96 offset between the two (4 * > > 32), is this expected? > > Yes, this is conform to the H3 documentation. Not really. The uart0 reset is the bit 16, in the reset register 4. 4 * 32 + 16 = 44. Not 112, but still not 208 either. Maxime -- Maxime Ripard, Free Electrons Embedded Linux, Kernel and Android engineering http://free-electrons.com
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