The "init" pinctrl is defined we'll set
pinctrl to this state before probe and then "default" after probe.
Add the "init" pinctrl as the OTP gpio state, since we need switch
the pin to gpio state before the TSADC controller is reset.
As I know, the TSADC controller is reset, the tshut polarity will be
a *low* signal in a short period of time for some devices.
Says:
The TSADC get the temperature on rockchip thermal.
If T(current temperature) < (setting temperature), the OTP output the
*high* signal.
If T(current temperature) > (setting temperature), the OTP output the
*low* Signal.
In some cases, the OTP pin is connected to the PMIC, maybe the
PMIC can accept the reset response time to avoid this issue.
In other words, the system will be always reboot if we make the
OTP pin is connected the others IC to control the power.
Signed-off-by: Caesar Wang <wxt@xxxxxxxxxxxxxx>
Reviewed-by: Douglas Anderson <dianders@xxxxxxxxxxxx>
---
Changes in v2:
- Add the 'init' pinctrl more decription in commit.
- Fix the subject to make more obvious in PATCH[1/2]
- Resend this patch v2 since fix the subject to be specific.
Changes in v1:
- As the Doug comments, add the 'init' property to sync document.
Documentation/devicetree/bindings/thermal/rockchip-thermal.txt | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/Documentation/devicetree/bindings/thermal/rockchip-thermal.txt b/Documentation/devicetree/bindings/thermal/rockchip-thermal.txt
index ef802de..28e84f7 100644
--- a/Documentation/devicetree/bindings/thermal/rockchip-thermal.txt
+++ b/Documentation/devicetree/bindings/thermal/rockchip-thermal.txt
@@ -27,8 +27,9 @@ tsadc: tsadc@ff280000 {
clock-names = "tsadc", "apb_pclk";
resets = <&cru SRST_TSADC>;
reset-names = "tsadc-apb";
- pinctrl-names = "default";
- pinctrl-0 = <&otp_out>;
+ pinctrl-names = "init", "default";
+ pinctrl-0 = <&otp_gpio>;
+ pinctrl-1 = <&otp_out>;
#thermal-sensor-cells = <1>;
rockchip,hw-tshut-temp = <95000>;
rockchip,hw-tshut-mode = <0>;
--
1.9.1
--
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