On Wed, Sep 9, 2015 at 4:07 AM, Arnd Bergmann <arnd@xxxxxxxx> wrote: > On Tuesday 08 September 2015 15:06:16 Li Yang wrote: >> On Mon, Sep 7, 2015 at 6:32 AM, Arnd Bergmann <arnd@xxxxxxxx> wrote: >> > On Friday 04 September 2015 12:27:46 Bhupesh Sharma wrote: >> >> @@ -4,7 +4,8 @@ This PCIe host controller is based on the Synopsis Designware PCIe IP >> >> and thus inherits all the common properties defined in designware-pcie.txt. >> >> >> >> Required properties: >> >> -- compatible: should contain the platform identifier such as "fsl,ls1021a-pcie" >> >> +- compatible: should contain the platform identifier such as "fsl,ls1021a-pcie", >> >> + "fsl,ls2080a-pcie". >> >> - reg: base addresses and lengths of the PCIe controller >> >> - interrupts: A list of interrupt outputs of the controller. Must contain an >> >> entry for each entry in the interrupt-names property. >> >> >> > >> > Are the two PCIe hosts mutually compatible? If they are, you should mandate >> > one of the strings as the base model for identification, with the additional >> > model being optional for identification of the specific SoC. >> >> It seems that controllers on these chips are not exactly the same. >> They will get different driver data by matching the compatible >> strings. Probably we could define a more generic compatible string, >> such as "fsl,layerscape-pcie" or "fsl,ls-pcie". >> >> > >> > It would also be good to add a string with the specific version number of the >> > designware PCIe block that is being used there. >> >> The binding has mentioned to reference the designware-pcie.txt. But >> it might be more clear to mention the designware compatible string >> "snps,dw-pcie" again in the compatible part. Currently there is no >> version number defined in the designware-pcie binding. It might be >> hard to get this information for some SoCs. > > For most of them, the information is available and then it should be > added. Obviously if you can't find it out, it's hard to guess and > you have to leave it out for that particular chip. Actually I don't know any approach to get the version number of the designware block used. Maybe they are actually using the same version of the IP block, and the differences in the driver are actually caused by the differences in SoC integration. > > A lot of devices also have some internal version register that you > can read out. There doesn't seem to be this kind of register for the PCIe block. Minghuan, Please correct me if you know more. :) Regards, Leo -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
