On Wednesday, August 26, 2015 at 02:30:25 PM, Cyrille Pitchen wrote: > The number of dummy cycles used during Fast Read commands can be reduced > to improve transfer performances. Each manufacturer has a dedicated set of > registers to provide the memory with the exact number of dummy cycles it > should expect. Both the memory and the (Q)SPI controller must agree on > this number of dummy cycles. > > The number of dummy cycles can be found into the memory datasheet and > mostly depends on the SPI clock frequency, the Fast Read op code and the > Single/Dual Data Rate mode. > > Probing JEDEC Serial Flash Discoverable Parameters (SFDP) tables would > only provide the driver with a high enough number of dummy cycles for each > Fast Read command to be used for all clock frequencies: this solution > would not be optimized. > > Signed-off-by: Cyrille Pitchen <cyrille.pitchen@xxxxxxxxx> Acked-by: Marek Vasut <marex@xxxxxxx> Best regards, Marek Vasut -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
