Describe the L1 caches in the CPU nodes:
- L1 instruction cache: 32 KiB (8 KiB x 4 ways) per CPU,
- L1 data cache: 32 KiB (8 KiB x 4 ways) per CPU.
Add links to the L2 cache.
Signed-off-by: Geert Uytterhoeven <geert+renesas@xxxxxxxxx>
---
v4:
- New.
---
arch/arm/boot/dts/sh73a0.dtsi | 18 ++++++++++++++++++
1 file changed, 18 insertions(+)
diff --git a/arch/arm/boot/dts/sh73a0.dtsi b/arch/arm/boot/dts/sh73a0.dtsi
index e84fce5e4090f4ab..34f45023d1d29ed0 100644
--- a/arch/arm/boot/dts/sh73a0.dtsi
+++ b/arch/arm/boot/dts/sh73a0.dtsi
@@ -28,6 +28,15 @@
reg = <0>;
clock-frequency = <1196000000>;
power-domains = <&pd_a2sl>;
+ i-cache-size = <0x8000>;
+ i-cache-sets = <256>;
+ i-cache-block-size = <32>;
+ i-cache-line-size = <32>;
+ d-cache-size = <0x8000>;
+ d-cache-sets = <256>;
+ d-cache-block-size = <32>;
+ d-cache-line-size = <32>;
+ next-level-cache = <&L2>;
};
cpu@1 {
device_type = "cpu";
@@ -35,6 +44,15 @@
reg = <1>;
clock-frequency = <1196000000>;
power-domains = <&pd_a2sl>;
+ i-cache-size = <0x8000>;
+ i-cache-sets = <256>;
+ i-cache-block-size = <32>;
+ i-cache-line-size = <32>;
+ d-cache-size = <0x8000>;
+ d-cache-sets = <256>;
+ d-cache-block-size = <32>;
+ d-cache-line-size = <32>;
+ next-level-cache = <&L2>;
};
};
--
1.9.1
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