On 20/11/15 16:14, Geert Uytterhoeven wrote:
Hi Sudeep,
[...]
AFAIK, there's nothing to be overridden. The cache seems to be configured in
the exact same way with and without cache-size, cache-sets, cache-block-size,
and cache-line-size.
With:
L2C OF: override cache size: 262144 bytes (256KB)
L2C OF: override line size: 32 bytes
L2C OF: override way size: 32768 bytes (32KB)
L2C OF: override associativity: 8
L2C: DT/platform modifies aux control register: 0x02040000 -> 0x02440000
L2C: DT/platform tries to modify or specify cache size
L2C-310 erratum 769419 enabled
L2C-310 enabling early BRESP for Cortex-A9
L2C-310 full line of zeros enabled for Cortex-A9
L2C-310 dynamic clock gating enabled, standby mode enabled
L2C-310 cache controller enabled, 8 ways, 256 kB
L2C-310: CACHE_ID 0x410000c7, AUX_CTRL 0x46440001
Without:
L2C: DT/platform modifies aux control register: 0x02040000 -> 0x02440000
L2C-310 erratum 769419 enabled
L2C-310 enabling early BRESP for Cortex-A9
L2C-310 full line of zeros enabled for Cortex-A9
L2C-310 dynamic clock gating enabled, standby mode enabled
L2C-310 cache controller enabled, 8 ways, 256 kB
L2C-310: CACHE_ID 0x410000c7, AUX_CTRL 0x46440001
Hence I'll drop cache-size, cache-sets, cache-block-size, and cache-line-size,
for both unified L2 and L1 I/D caches.
Sorry for the delay, was on vacation. Looks fine for me.
--
Regards,
Sudeep
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