On Thursday, July 16, 2015 at 05:27:51 PM, Cyrille Pitchen wrote: Hi! > Both the SPI controller and the NOR flash memory need to agree on the > number of dummy cycles to use for Fast Read commands. For Spansion > memories, this number of dummy cycles is not given directly but through a > so called "latency code". > The latency code can be found into the memory datasheet and depends on the > SPI clock frequency, the Fast Read op code and the Single/Dual Data Rate > mode. Shouldn't you be able to derive the latency code from the above information, which you already know then ? Best regards, Marek Vasut -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
