On Friday 10 July 2015 08:26 PM, Wolfram Sang wrote:
On Fri, Jul 10, 2015 at 07:55:31PM +0530, Vaibhav Hiremath wrote:
On Friday 10 July 2015 07:44 PM, Wolfram Sang wrote:
On Fri, Jul 10, 2015 at 06:08:43PM +0530, Vaibhav Hiremath wrote:
On Friday 10 July 2015 01:41 PM, Wolfram Sang wrote:
On Tue, Jul 07, 2015 at 12:54:46AM +0530, Vaibhav Hiremath wrote:
Normally i2c controller works as master, so slave addr is not needed, or it
will impact some slave device (eg. ST NFC chip) i2c accesses, because it has
the same i2c address with controller.
Just to make sure: Does it? As I read the code, slave interrupts are
enabled later only when slave mode is selected? Is that a HW bug? And if
so, can't the code just be moved into this #ifdef block later?
Yes we could, infact I thought about it;
but I would break recommended sequence here.
And did you set the "own slave address" to a value which one of your
existing i2c slaves also has (without enabling slave mode)? Did it
disturb communication?
Since slave and master mode are mutual exclusive,
I did not try this.
Ehrm, what I meant was. Did you see the issue mentioned in the above
commit message? Can you reproduce it? You don't need to enable slave
mode for that, no?
Ohh yes,
I am able to reproduce this issue.
I have pxa1928 based board, where I have only PMIC 88PM860 connected to
I2C bus, and whenever I set slave address to 0x30 (PMIC slave address)
all I2C transaction for PMIC goes for toss.
Thanks,
Vaibhav
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