On Tue, Jun 09, 2015 at 01:53:54PM +0200, Cyrille Pitchen wrote: > To enable the FIFO feature a "atmel,fifo-size" attribute with a strictly > positive value must be added into the node of the device-tree describing > the spi controller. I'd expect the driver to use FIFOs any time they make sense, I wouldn't expect this to be something that requires configuration - I'd expect that there's going to be at least some FIFO in all versions of the IP, even if the size varies. Is that not the case? > When FIFOs are enabled, the RX one is forced to operate in SINGLE data > mode because this driver configures the spi controller as a master. In > master mode only, the Received Data Register has an additionnal Peripheral > Chip Select field, which prevents us from reading more than a single data > at each register access. > > Besides, the TX FIFO operates in MULTIPLE data mode. However, even when a This is very hard to understand as I have no idea what single and multiple data modes are, sorry. Please write your commit messages so they can be read by people who aren't familiar with the internals of the IP.
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