On 3/17/2025 8:25 AM, Bjorn Andersson wrote: > > On Tue, 12 Nov 2024 18:14:10 +0530, Jagadeesh Kona wrote: >> Add support to scale DDR and L3 frequencies >> based on CPU frequencies on Qualcomm SA8775P >> platform. Also add LMH interrupts in cpufreq_hw >> node to indicate if there is any thermal throttle. >> >> The changes in this series are dependent on below series changes: >> https://lore.kernel.org/all/20241112075826.28296-1-quic_rlaggysh@xxxxxxxxxxx/ >> >> [...] > > Applied, thanks! > > [1/2] arm64: dts: qcom: sa8775p: Add CPU OPP tables to scale DDR/L3 > (no commit info) Hi Bjorn, I am not sure if above DDR/L3 scaling commit is picked here, but as per our earlier discussion[1], I have included the above patch in the dependent interconnect series[2]. Above DDR/L3 scaling patch cannot be picked alone without interconnect changes, as it will lead to compilation errors. [1]: https://lore.kernel.org/all/d649eac7-c9bb-48f9-a5d7-758688b85107@xxxxxxxxxxx/ [2]: https://lore.kernel.org/all/20250227155213.404-1-quic_rlaggysh@xxxxxxxxxxx/ Thanks, Jagadeesh > [2/2] arm64: dts: qcom: sa8775p: Add LMH interrupts for cpufreq_hw node > commit: cc13a858a79d8c5798a99e8cde677ea36272a5a0 > > Best regards,
