On Wed, 05 Mar 2025, Fabrice Gasnier wrote: > Add support for STM32MP25 SoC. > A new hardware configuration register (HWCFGR2) has been added, to gather > number of capture/compare channels, autonomous mode and input capture > capability. The full feature set is implemented in LPTIM1/2/3/4. LPTIM5 > supports a smaller set of features. This can now be read from HWCFGR > registers. > > Add new registers to the stm32-lptimer.h: CCMR1, CCR2, HWCFGR1/2 and VERR. > Update the stm32_lptimer data struct so signal the number of > capture/compare channels to the child devices. > Also Remove some unused bit masks (CMPOK_ARROK / CMPOKCF_ARROKCF). > > Signed-off-by: Fabrice Gasnier <fabrice.gasnier@xxxxxxxxxxx> > --- > Changes in V2: > - rely on fallback compatible as no specific .data is associated to the > driver. Compatibility is added by reading hardware configuration > registers. > - read version register, to be used by clockevent child driver > - rename register/bits definitions > --- > drivers/mfd/stm32-lptimer.c | 33 ++++++++++++++++++++++++++++- Looks okay. > include/linux/mfd/stm32-lptimer.h | 35 ++++++++++++++++++++++++++++--- Assumingly this patch is not independent of the others? -- Lee Jones [李琼斯]
