Hi again Frank!
I've now tested this patch-set together with your v9 on-top of the
next-branch of the pci tree, and seems to be working good on my
ARTPEC-6 set as RC:
# lspci
00:00.0 PCI bridge: Renesas Technology Corp. Device 0024
01:00.0 PCI bridge: Pericom Semiconductor PI7C9X2G304 EL/SL PCIe2 3-Port/4-Lane Packet Switch (rev 05)
02:01.0 PCI bridge: Pericom Semiconductor PI7C9X2G304 EL/SL PCIe2 3-Port/4-Lane Packet Switch (rev 05)
02:02.0 PCI bridge: Pericom Semiconductor PI7C9X2G304 EL/SL PCIe2 3-Port/4-Lane Packet Switch (rev 05)
03:00.0 Non-Volatile memory controller: Phison Electronics Corporation E18 PCIe4 NVMe Controller (rev 01)
However, when running as EP, I found that the DT setup for pcie_ep
wasn't correct:
diff --git a/arch/arm/boot/dts/axis/artpec6.dtsi b/arch/arm/boot/dts/axis/artpec6.dtsi
index 399e87f72865..6d52f60d402d 100644
--- a/arch/arm/boot/dts/axis/artpec6.dtsi
+++ b/arch/arm/boot/dts/axis/artpec6.dtsi
@@ -195,8 +195,8 @@ pcie: pcie@f8050000 {
pcie_ep: pcie_ep@f8050000 {
compatible = "axis,artpec6-pcie-ep", "snps,dw-pcie";
- reg = <0xf8050000 0x2000
- 0xf8051000 0x2000
+ reg = <0xf8050000 0x1000
+ 0xf8051000 0x1000
0xf8040000 0x1000
0x00000000 0x20000000>;
reg-names = "dbi", "dbi2", "phy", "addr_space";
Even with this fix, I get a panic in dw_pcie_read_dbi() in EP-setup,
both with and without:
"PCI: artpec6: Use use_parent_dt_ranges and clean up artpec6_pcie_cpu_addr_fixup()"
so it looks like the ARTPEC-6 EP functionality wasn't completely tested
with this config.
The ARTPEC-7 variant does work as EP with our local config, I'll try
to see what I can do to correct ARTPEC-6 using the setup for ARTPEC-7,
and test your patchset on the ARTPEC-7.
Best regards,
/Jesper
On Wed, Mar 05, 2025 at 04:33:18PM +0100, Jesper Nilsson wrote:
> Hi Frank,
>
> I'm the current maintainer of this driver. As Niklas Cassel wrote in
> another email, artpec-7 was supposed to be upstreamed, as it is in most
> parts identical to the artpec-6, but reality got in the way. I don't
> think there is very much left to support it at the same level as artpec-6,
> but give me some time to see if the best thing is to drop the artpec-7
> support as Niklas suggested.
>
> Unfortunately, I'm travelling right now and don't have access to any
> of my boards. I'll perform some testing next week when I'm back and
> help to clean this up.
>
> Best regards,
>
> /Jesper
>
>
> On Tue, Mar 04, 2025 at 12:49:34PM -0500, Frank Li wrote:
> > This patches basic on
> > https://lore.kernel.org/imx/20250128-pci_fixup_addr-v9-0-3c4bb506f665@xxxxxxx/
> >
> > I have not hardware to test and there are not axis,artpec7-pcie in kernel
> > tree.
> >
> > Look for driver owner, who help test this and start move forward to remove
> > cpu_addr_fixup() work.
> >
> > Signed-off-by: Frank Li <Frank.Li@xxxxxxx>
> > ---
> > Frank Li (2):
> > ARM: dts: artpec6: Move PCIe nodes under bus@c0000000
> > PCI: artpec6: Use use_parent_dt_ranges and clean up artpec6_pcie_cpu_addr_fixup()
> >
> > arch/arm/boot/dts/axis/artpec6.dtsi | 92 +++++++++++++++++--------------
> > drivers/pci/controller/dwc/pcie-artpec6.c | 20 +------
> > 2 files changed, 52 insertions(+), 60 deletions(-)
> > ---
> > base-commit: 1552be4855dacca5ea39b15b1ef0b96c91dbea0d
> > change-id: 20250304-axis-6d12970976b4
> >
> > Best regards,
> > ---
> > Frank Li <Frank.Li@xxxxxxx>
>
> /^JN - Jesper Nilsson
> --
> Jesper Nilsson -- jesper.nilsson@xxxxxxxx
/^JN - Jesper Nilsson
--
Jesper Nilsson -- jesper.nilsson@xxxxxxxx
