On Thu, Mar 06, 2025 at 05:57:51PM +0000, Haylen Chu wrote:
> Describe the PLL and system controllers that're capable of generating
> clock signals in the devicetree.
>
> Signed-off-by: Haylen Chu <heylenay@xxxxxxx>
> ---
> arch/riscv/boot/dts/spacemit/k1.dtsi | 79 ++++++++++++++++++++++++++++
> 1 file changed, 79 insertions(+)
>
> diff --git a/arch/riscv/boot/dts/spacemit/k1.dtsi b/arch/riscv/boot/dts/spacemit/k1.dtsi
> index c670ebf8fa12..09a9100986b1 100644
> --- a/arch/riscv/boot/dts/spacemit/k1.dtsi
> +++ b/arch/riscv/boot/dts/spacemit/k1.dtsi
> @@ -3,6 +3,8 @@
> * Copyright (C) 2024 Yangyu Chen <cyy@xxxxxxxxxxxx>
> */
>
> +#include <dt-bindings/clock/spacemit,k1-ccu.h>
> +
> /dts-v1/;
> / {
> #address-cells = <2>;
> @@ -306,6 +308,40 @@ cluster1_l2_cache: l2-cache1 {
> };
> };
>
> + clocks {
> + #address-cells = <0x2>;
> + #size-cells = <0x2>;
> + ranges;
why setting this?
> +
> + vctcxo_1m: clock-1m {
> + compatible = "fixed-clock";
> + clock-frequency = <1000000>;
Should the frequency this move to the board file?
I do not think these clock are in the soc.
This applys to all clock below.
> + clock-output-names = "vctcxo_1m";
> + #clock-cells = <0>;
> + };
> +
> + vctcxo_24m: clock-24m {
> + compatible = "fixed-clock";
> + clock-frequency = <24000000>;
> + clock-output-names = "vctcxo_24m";
> + #clock-cells = <0>;
> + };
> +
> + vctcxo_3m: clock-3m {
> + compatible = "fixed-clock";
> + clock-frequency = <3000000>;
> + clock-output-names = "vctcxo_3m";
> + #clock-cells = <0>;
> + };
> +
> + osc_32k: clock-32k {
> + compatible = "fixed-clock";
> + clock-frequency = <32000>;
> + clock-output-names = "osc_32k";
> + #clock-cells = <0>;
> + };
> + };
> +
> soc {
> compatible = "simple-bus";
> interrupt-parent = <&plic>;
> @@ -314,6 +350,17 @@ soc {
> dma-noncoherent;
> ranges;
>
> + syscon_apbc: system-control@d4015000 {
> + compatible = "spacemit,k1-syscon-apbc";
> + reg = <0x0 0xd4015000 0x0 0x1000>;
> + clocks = <&osc_32k>, <&vctcxo_1m>, <&vctcxo_3m>,
> + <&vctcxo_24m>;
> + clock-names = "osc", "vctcxo_1m", "vctcxo_3m",
> + "vctcxo_24m";
> + #clock-cells = <1>;
> + #reset-cells = <1>;
> + };
> +
> uart0: serial@d4017000 {
> compatible = "spacemit,k1-uart", "intel,xscale-uart";
> reg = <0x0 0xd4017000 0x0 0x100>;
> @@ -409,6 +456,38 @@ pinctrl: pinctrl@d401e000 {
> reg = <0x0 0xd401e000 0x0 0x400>;
> };
>
> + syscon_mpmu: system-controller@d4050000 {
> + compatible = "spacemit,k1-syscon-mpmu";
> + reg = <0x0 0xd4050000 0x0 0x209c>;
> + clocks = <&osc_32k>, <&vctcxo_1m>, <&vctcxo_3m>,
> + <&vctcxo_24m>;
> + clock-names = "osc", "vctcxo_1m", "vctcxo_3m",
> + "vctcxo_24m";
> + #clock-cells = <1>;
> + #power-domain-cells = <1>;
> + #reset-cells = <1>;
> + };
> +
> + pll: system-control@d4090000 {
> + compatible = "spacemit,k1-pll";
> + reg = <0x0 0xd4090000 0x0 0x1000>;
> + clocks = <&vctcxo_24m>;
> + spacemit,mpmu = <&syscon_mpmu>;
> + #clock-cells = <1>;
> + };
> +
> + syscon_apmu: system-control@d4282800 {
> + compatible = "spacemit,k1-syscon-apmu";
> + reg = <0x0 0xd4282800 0x0 0x400>;
> + clocks = <&osc_32k>, <&vctcxo_1m>, <&vctcxo_3m>,
> + <&vctcxo_24m>;
> + clock-names = "osc", "vctcxo_1m", "vctcxo_3m",
> + "vctcxo_24m";
> + #clock-cells = <1>;
> + #power-domain-cells = <1>;
> + #reset-cells = <1>;
> + };
> +
> plic: interrupt-controller@e0000000 {
> compatible = "spacemit,k1-plic", "sifive,plic-1.0.0";
> reg = <0x0 0xe0000000 0x0 0x4000000>;
> --
> 2.48.1
>
