On Wed, May 06, 2015 at 11:12:20AM -0700, Loc Ho wrote:
> 1. Whether to have an single driver for APM EDAC or multiple instance
> of 4 different drivers. With single driver, it does not scale in the
> future when we add/remove memory controllers and CPU domains. This is
Why doesn't it scale? Please explain this to me more verbosely.
> also agreed by Rob Herring from review of the DTS nodes. For L3 and
> SoC EDAC, they are less of an issue as I don't see a situation that we
> would have multiple instances.
>
> 2. With regard to the top level PCP interrupt, they are just for
> status and once configured, it will not be touch. Therefore, I keep
> the current implementation. With an single driver, there is no need to
> worry about read/modify/write as it will be guarded with an lock. For
> multiple instance, I am thinking that the xgene_edac_mc module will
> provide exported lock functions for the other drivers.
Doing this would be a very bad design and it would be a homegrown case
only for this driver. Then other ARM drivers will appear which will do
their own locking too. No no no. No ad-hoc hackery.
--
Regards/Gruss,
Boris.
ECO tip #101: Trim your mails when you reply.
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