On Mon, Mar 03, 2025 at 03:37:44PM +0000, Hugues KAMBA MPIANA wrote:
> Add `cpu1`, `cpu2` and `cpu3` nodes to the Corstone1000 device tree to
> enable support for secondary CPU cores.
>
> This update facilitates symmetric multiprocessing (SMP) support on
> the Corstone1000 Fixed Virtual Platform (FVP), allowing the
> secondary cores to be properly initialised and utilised.
>
> Signed-off-by: Hugues KAMBA MPIANA <hugues.kambampiana@xxxxxxx>
> ---
> arch/arm64/boot/dts/arm/corstone1000-fvp.dts | 24 ++++++++++++++++++++
> arch/arm64/boot/dts/arm/corstone1000.dtsi | 2 +-
> 2 files changed, 25 insertions(+), 1 deletion(-)
>
> diff --git a/arch/arm64/boot/dts/arm/corstone1000-fvp.dts b/arch/arm64/boot/dts/arm/corstone1000-fvp.dts
> index abd013562995..df9700302b8d 100644
> --- a/arch/arm64/boot/dts/arm/corstone1000-fvp.dts
> +++ b/arch/arm64/boot/dts/arm/corstone1000-fvp.dts
> @@ -49,3 +49,27 @@ sdmmc1: mmc@50000000 {
> clock-names = "smclk", "apb_pclk";
> };
> };
> +
> +&cpus {
> + cpu1: cpu@1 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a35";
> + reg = <0x1>;
> + enable-method = "psci";
> + next-level-cache = <&L2_0>;
> + };
> + cpu2: cpu@2 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a35";
> + reg = <0x2>;
> + enable-method = "psci";
> + next-level-cache = <&L2_0>;
> + };
> + cpu3: cpu@3 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a35";
> + reg = <0x3>;
> + enable-method = "psci";
> + next-level-cache = <&L2_0>;
> + };
Why are these not part of /cpus node in corstone1000.dtsi ?
Also I see the original cpu@0 node doesn't have enable-method set to
"psci" while these secondary cpus have. Please add the same and move all
these changes in corstone1000.dtsi unless you have strong reasons not to.
In that case, please clearly state the reason in the commit message.
P.S: I was about to send PR soon for v6.15. If you want this change for
v6.15, you need to be quicker.
--
Regards,
Sudeep
