This patch adds documentation for the APM X-Gene SoC EDAC DTS binding.
Signed-off-by: Feng Kan <fkan@xxxxxxx>
Signed-off-by: Loc Ho <lho@xxxxxxx>
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.../devicetree/bindings/edac/apm-xgene-edac.txt | 50 ++++++++++++++++++++
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create mode 100644 Documentation/devicetree/bindings/edac/apm-xgene-edac.txt
diff --git a/Documentation/devicetree/bindings/edac/apm-xgene-edac.txt b/Documentation/devicetree/bindings/edac/apm-xgene-edac.txt
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+* APM X-Gene SoC EDAC nodes
+
+EDAC nodes are defined to describe on-chip error detection and correction.
+The follow type is supported:
+
+ memory controller - Memory controller
+
+The following section describes the memory controller DT node binding.
+
+Required properties:
+- compatible : Shall be "apm,xgene-edac-mc".
+- regmap-pcp : Regmap of the CPU bus (PCP) resource.
+- regmap-csw : Regmap of the CPU switch fabric (CSW) resource.
+- regmap-mcba : Regmap of the MCB-A (memory bridge) resource.
+- regmap-mcbb : Regmap of the MCB-B (memory bridge) resource.
+- reg : First resource shall be the memory controller unit
+ (MCU) resource.
+- interrupts : Interrupt-specifier for MCU error IRQ(s).
+
+Example:
+ pcp: pcp@78800000 {
+ compatible = "syscon";
+ reg = <0x0 0x78800000 0x0 0x100>;
+ };
+
+ csw: csw@7e200000 {
+ compatible = "syscon";
+ reg = <0x0 0x7e200000 0x0 0x1000>;
+ };
+
+ mcba: mcba@7e700000 {
+ compatible = "syscon";
+ reg = <0x0 0x7e700000 0x0 0x1000>;
+ };
+
+ mcbb: mcbb@7e720000 {
+ compatible = "syscon";
+ reg = <0x0 0x7e720000 0x0 0x1000>;
+ };
+
+ edacmc0: edacmc0@7e800000 {
+ compatible = "apm,xgene-edac-mc";
+ regmap-pcp = <&pcp>;
+ regmap-csw = <&csw>;
+ regmap-mcba = <&mcba>;
+ regmap-mcbb = <&mcbb>;
+ reg = <0x0 0x7e800000 0x0 0x1000>;
+ interrupts = <0x0 0x20 0x4>,
+ <0x0 0x21 0x4>;
+ };
--
1.7.1
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