Sven Peter 於 2025/3/1 夜晚7:11 寫道: > Hi, > > On Thu, Feb 20, 2025, at 13:21, Nick Chan wrote: >> Add CPU cache information for Apple A7-A11, T2 SoCs. On Apple >> A10 (T8010), A10X (T8011), T2 (T8012), only the caches in one of the >> CPU clusters can be used due to the "Apple Fusion Architecture" >> big.LITTLE switcher. The values for the P-cluster is used in this >> case. > So this means that the cache information will be "wrong" when the CPU > is in the lower power states and only correct for the higher ones? > I'm not familiar with how these values are used; are you and do you > know if this will have any weird or unexpected effects? > Would it be better to use the cache size for the lower rather than > the higher states or does this not matter much? The information in the device tree is only used for reporting cache sizes in /sys/devices/system/cpu. It represents the physical cache size which may not be the same as the architecturally visible cache size. Cache operations in the kernel consult ccsidr_el1 and csselr_el1, so it should be fine. > > > > Best, > > > Sven Nick Chan
