Hi, On Thu, Feb 20, 2025, at 13:21, Nick Chan wrote: > Add CPU cache information for Apple A7-A11, T2 SoCs. On Apple > A10 (T8010), A10X (T8011), T2 (T8012), only the caches in one of the > CPU clusters can be used due to the "Apple Fusion Architecture" > big.LITTLE switcher. The values for the P-cluster is used in this > case. So this means that the cache information will be "wrong" when the CPU is in the lower power states and only correct for the higher ones? I'm not familiar with how these values are used; are you and do you know if this will have any weird or unexpected effects? Would it be better to use the cache size for the lower rather than the higher states or does this not matter much? Best, Sven
