Hi Marek,
Am Donnerstag, 27. Februar 2025, 17:58:09 CET schrieb Marek Vasut:
> The instance of the GPU populated in i.MX95 is the G310,
> describe this GPU in the DT. Include description of the
> GPUMIX block controller, which can be operated as a simple
> reset. Include dummy GPU voltage regulator and OPP tables.
>
> Signed-off-by: Marek Vasut <marex@xxxxxxx>
> ---
> Cc: Boris Brezillon <boris.brezillon@xxxxxxxxxxxxx>
> Cc: Conor Dooley <conor+dt@xxxxxxxxxx>
> Cc: David Airlie <airlied@xxxxxxxxx>
> Cc: Fabio Estevam <festevam@xxxxxxxxx>
> Cc: Krzysztof Kozlowski <krzk+dt@xxxxxxxxxx>
> Cc: Liviu Dudau <liviu.dudau@xxxxxxx>
> Cc: Maarten Lankhorst <maarten.lankhorst@xxxxxxxxxxxxxxx>
> Cc: Maxime Ripard <mripard@xxxxxxxxxx>
> Cc: Pengutronix Kernel Team <kernel@xxxxxxxxxxxxxx>
> Cc: Philipp Zabel <p.zabel@xxxxxxxxxxxxxx>
> Cc: Rob Herring <robh@xxxxxxxxxx>
> Cc: Sascha Hauer <s.hauer@xxxxxxxxxxxxxx>
> Cc: Sebastian Reichel <sre@xxxxxxxxxx>
> Cc: Shawn Guo <shawnguo@xxxxxxxxxx>
> Cc: Simona Vetter <simona@xxxxxxxx>
> Cc: Steven Price <steven.price@xxxxxxx>
> Cc: Thomas Zimmermann <tzimmermann@xxxxxxx>
> Cc: devicetree@xxxxxxxxxxxxxxx
> Cc: dri-devel@xxxxxxxxxxxxxxxxxxxxx
> Cc: imx@xxxxxxxxxxxxxxx
> Cc: linux-arm-kernel@xxxxxxxxxxxxxxxxxxx
> ---
> arch/arm64/boot/dts/freescale/imx95.dtsi | 62 ++++++++++++++++++++++++
> 1 file changed, 62 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/freescale/imx95.dtsi b/arch/arm64/boot/dts/freescale/imx95.dtsi
> index 3af13173de4bd..36bad211e5558 100644
> --- a/arch/arm64/boot/dts/freescale/imx95.dtsi
> +++ b/arch/arm64/boot/dts/freescale/imx95.dtsi
> @@ -249,6 +249,37 @@ dummy: clock-dummy {
> clock-output-names = "dummy";
> };
>
> + gpu_fixed_reg: fixed-gpu-reg {
> + compatible = "regulator-fixed";
> + regulator-min-microvolt = <920000>;
> + regulator-max-microvolt = <920000>;
> + regulator-name = "vdd_gpu";
> + regulator-always-on;
> + regulator-boot-on;
> + };
Is this an internal voltage?
> +
> + gpu_opp_table: opp_table {
Node-Names use dash instead of underscore.
> + compatible = "operating-points-v2";
> +
> + opp-500000000 {
> + opp-hz = /bits/ 64 <500000000>;
> + opp-hz-real = /bits/ 64 <500000000>;
> + opp-microvolt = <920000>;
> + };
> +
> + opp-800000000 {
> + opp-hz = /bits/ 64 <800000000>;
> + opp-hz-real = /bits/ 64 <800000000>;
> + opp-microvolt = <920000>;
> + };
> +
> + opp-1000000000 {
> + opp-hz = /bits/ 64 <1000000000>;
> + opp-hz-real = /bits/ 64 <1000000000>;
> + opp-microvolt = <920000>;
> + };
> + };
> +
> clk_ext1: clock-ext1 {
> compatible = "fixed-clock";
> #clock-cells = <0>;
> @@ -1846,6 +1877,37 @@ netc_emdio: mdio@0,0 {
> };
> };
>
> + gpu_blk_ctrl: reset-controller@4d810000 {
> + compatible = "fsl,imx95-gpu-blk-ctrl";
> + reg = <0x0 0x4d810000 0x0 0xc>;
Mh, GPU_BLK_CTRL is /just a bit) more than the GPU reset. Does it make sense
to make this an gpu-reset-only node, located at 0x4d810008?
> + #reset-cells = <1>;
> + clocks = <&scmi_clk IMX95_CLK_GPUAPB>;
> + assigned-clocks = <&scmi_clk IMX95_CLK_GPUAPB>;
> + assigned-clock-parents = <&scmi_clk IMX95_CLK_SYSPLL1_PFD1_DIV2>;
> + assigned-clock-rates = <133333333>;
> + power-domains = <&scmi_devpd IMX95_PD_GPU>;
> + status = "disabled";
> + };
> +
> + gpu: gpu@4d900000 {
> + compatible = "fsl,imx95-mali", "arm,mali-valhall-csf";
> + reg = <0 0x4d900000 0 0x480000>;
> + clocks = <&scmi_clk IMX95_CLK_GPU>;
There is also IMX95_CLK_GPUAPB. Is this only required for the rese control above?
> + clock-names = "core";
> + interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 289 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-names = "gpu", "job", "mmu";
DT bindings say this order: job, mmu, gpu
Best regards
Alexander
> + mali-supply = <&gpu_fixed_reg>;
> + operating-points-v2 = <&gpu_opp_table>;
> + power-domains = <&scmi_devpd IMX95_PD_GPU>, <&scmi_perf IMX95_PERF_GPU>;
> + power-domain-names = "mix", "perf";
> + resets = <&gpu_blk_ctrl 0>;
> + #cooling-cells = <2>;
> + dynamic-power-coefficient = <1013>;
> + status = "disabled";
> + };
> +
> ddr-pmu@4e090dc0 {
> compatible = "fsl,imx95-ddr-pmu", "fsl,imx93-ddr-pmu";
> reg = <0x0 0x4e090dc0 0x0 0x200>;
>
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