On Fri, Feb 21, 2025 at 11:04:51AM -0600, Matthew Gerlach wrote: > Add the compatible bindings for the three variants of Agilex > PCIe Hard IP. > > Signed-off-by: Matthew Gerlach <matthew.gerlach@xxxxxxxxxxxxxxx> Acked-by: Manivannan Sadhasivam <manivannan.sadhasivam@xxxxxxxxxx> - Mani > Reviewed-by: Rob Herring (Arm) <robh@xxxxxxxxxx> > --- > v8: > - Removed patches unrelated to Agilex PCIe root port support from set. > - Removed patches related to a specific FPGA configuration from set. > --- > .../devicetree/bindings/pci/altr,pcie-root-port.yaml | 10 ++++++++++ > 1 file changed, 10 insertions(+) > > diff --git a/Documentation/devicetree/bindings/pci/altr,pcie-root-port.yaml b/Documentation/devicetree/bindings/pci/altr,pcie-root-port.yaml > index 52533fccc134..1f93120d8eef 100644 > --- a/Documentation/devicetree/bindings/pci/altr,pcie-root-port.yaml > +++ b/Documentation/devicetree/bindings/pci/altr,pcie-root-port.yaml > @@ -12,9 +12,19 @@ maintainers: > > properties: > compatible: > + description: Each family of socfpga has its own implementation > + of the pci controller. altr,pcie-root-port-1.0 is used for the Cyclone5 > + family of chips. The Stratix10 family of chips is supported > + by altr,pcie-root-port-2.0. The Agilex family of chips has > + three, non-register compatible, variants of PCIe Hard IP referred to as > + the f-tile, p-tile, and r-tile, depending on the specific chip instance. > + > enum: > - altr,pcie-root-port-1.0 > - altr,pcie-root-port-2.0 > + - altr,pcie-root-port-3.0-f-tile > + - altr,pcie-root-port-3.0-p-tile > + - altr,pcie-root-port-3.0-r-tile > > reg: > items: > -- > 2.34.1 > -- மணிவண்ணன் சதாசிவம்
