SM8750 have two different clusters. cluster0 have CPU 0-5 as child and
cluster1 have CPU 6-7 as child. Each cluster requires its own idle state
and power domain in order to achieve complete domain sleep state.
However only single cluster idle state is added mapping CPU 0-7 to the
same power domain. Fix this by correctly mapping each CPU to respective
cluster power domain and add domain idle state for cluster1.
Fixes: 068c3d3c83be ("arm64: dts: qcom: Add base SM8750 dtsi")
Signed-off-by: Maulik Shah <maulik.shah@xxxxxxxxxxxxxxxx>
---
arch/arm64/boot/dts/qcom/sm8750.dtsi | 36 +++++++++++++++++++++++++-----------
1 file changed, 25 insertions(+), 11 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/sm8750.dtsi b/arch/arm64/boot/dts/qcom/sm8750.dtsi
index 3bbd7d18598ee0a3a0d5130c03a3166e1fc14d82..3af928be5b68b47988dd55f4add8e3712f07d5ab 100644
--- a/arch/arm64/boot/dts/qcom/sm8750.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8750.dtsi
@@ -178,7 +178,15 @@ cluster1_c4: cpu-sleep-1 {
};
domain-idle-states {
- cluster_cl5: cluster-sleep-0 {
+ cluster0_cl5: cluster-sleep-0 {
+ compatible = "domain-idle-state";
+ arm,psci-suspend-param = <0x01000054>;
+ entry-latency-us = <2150>;
+ exit-latency-us = <1983>;
+ min-residency-us = <9144>;
+ };
+
+ cluster1_cl5: cluster-sleep-1 {
compatible = "domain-idle-state";
arm,psci-suspend-param = <0x01000054>;
entry-latency-us = <2150>;
@@ -233,55 +241,61 @@ psci {
cpu_pd0: power-domain-cpu0 {
#power-domain-cells = <0>;
- power-domains = <&cluster_pd>;
+ power-domains = <&cluster0_pd>;
domain-idle-states = <&cluster0_c4>;
};
cpu_pd1: power-domain-cpu1 {
#power-domain-cells = <0>;
- power-domains = <&cluster_pd>;
+ power-domains = <&cluster0_pd>;
domain-idle-states = <&cluster0_c4>;
};
cpu_pd2: power-domain-cpu2 {
#power-domain-cells = <0>;
- power-domains = <&cluster_pd>;
+ power-domains = <&cluster0_pd>;
domain-idle-states = <&cluster0_c4>;
};
cpu_pd3: power-domain-cpu3 {
#power-domain-cells = <0>;
- power-domains = <&cluster_pd>;
+ power-domains = <&cluster0_pd>;
domain-idle-states = <&cluster0_c4>;
};
cpu_pd4: power-domain-cpu4 {
#power-domain-cells = <0>;
- power-domains = <&cluster_pd>;
+ power-domains = <&cluster0_pd>;
domain-idle-states = <&cluster0_c4>;
};
cpu_pd5: power-domain-cpu5 {
#power-domain-cells = <0>;
- power-domains = <&cluster_pd>;
+ power-domains = <&cluster0_pd>;
domain-idle-states = <&cluster0_c4>;
};
cpu_pd6: power-domain-cpu6 {
#power-domain-cells = <0>;
- power-domains = <&cluster_pd>;
+ power-domains = <&cluster1_pd>;
domain-idle-states = <&cluster1_c4>;
};
cpu_pd7: power-domain-cpu7 {
#power-domain-cells = <0>;
- power-domains = <&cluster_pd>;
+ power-domains = <&cluster1_pd>;
domain-idle-states = <&cluster1_c4>;
};
- cluster_pd: power-domain-cluster {
+ cluster0_pd: power-domain-cluster0 {
+ #power-domain-cells = <0>;
+ domain-idle-states = <&cluster0_cl5>;
+ power-domains = <&system_pd>;
+ };
+
+ cluster1_pd: power-domain-cluster1 {
#power-domain-cells = <0>;
- domain-idle-states = <&cluster_cl5>;
+ domain-idle-states = <&cluster1_cl5>;
power-domains = <&system_pd>;
};
---
base-commit: e5d3fd687aac5eceb1721fa92b9f49afcf4c3717
change-id: 20250218-sm8750_cluster_idle-6fe358eb8c7e
Best regards,
--
Maulik Shah <maulik.shah@xxxxxxxxxxxxxxxx>
