On 14.02.2025 9:48 AM, Krishna Chaitanya Chundru wrote: > > > On 2/14/2025 2:14 PM, Manivannan Sadhasivam wrote: >> On Mon, Feb 10, 2025 at 01:00:00PM +0530, Krishna Chaitanya Chundru wrote: >>> Add PCIe lane equalization preset properties for 8 GT/s and 16 GT/s data >>> rates used in lane equalization procedure. >>> >>> Signed-off-by: Krishna Chaitanya Chundru <krishna.chundru@xxxxxxxxxxxxxxxx> >>> --- >>> This patch depends on the this dt binding pull request which got recently >>> merged: https://github.com/devicetree-org/dt-schema/pull/146 >>> --- >>> --- >>> arch/arm64/boot/dts/qcom/x1e80100.dtsi | 13 +++++++++++++ >>> 1 file changed, 13 insertions(+) >>> >>> diff --git a/arch/arm64/boot/dts/qcom/x1e80100.dtsi b/arch/arm64/boot/dts/qcom/x1e80100.dtsi >>> index 4936fa5b98ff..1b815d4eed5c 100644 >>> --- a/arch/arm64/boot/dts/qcom/x1e80100.dtsi >>> +++ b/arch/arm64/boot/dts/qcom/x1e80100.dtsi >>> @@ -3209,6 +3209,11 @@ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, >>> phys = <&pcie3_phy>; >>> phy-names = "pciephy"; >>> + eq-presets-8gts = /bits/ 16 <0x5555 0x5555 0x5555 0x5555>, >>> + /bits/ 16 <0x5555 0x5555 0x5555 0x5555>; >> >> Why 2 16bit arrays? >> > Just to keep line length below 100, if I use single line it is crossing > 100 lines. Oh I didn't notice this.. Ideally we would have <A0>, <A1>, ..., <An>; But it seems like /bits/ applies individually to each entry? That's a bit weird, but I'll add it to my list of things I don't like about dtc.. Let's do: eq-presets-8gts = /bits/ 16 <0x5555 0x5555 0x5555 0x5555 0x5555 0x5555 0x5555 0x5555>; for now Konrad
