On Wed, Apr 29, 2015 at 4:56 PM, Loc Ho <lho@xxxxxxx> wrote: > Hi, > >>> > Similar comments for the rest. I would define memory controller >>> > bindings and EDAC driver, then worry about the rest. >>> >>> Okay.. As comment in following emails, I will break up the driver into >>> multiple drivers and focus only on the memory controller driver first. >> >> Please no multiple EDAC drivers. Or do you mean something else here? > > We will have the following: > > xgene-edac-mc.c > xgene-edac-pmd.c > xgene-edac-l3.c > xgene-edac-soc.c > > Or what would you suggest. There are the following HW: > > 1. 4 DDR controller with one shared top level interrupt, two shared > memory bridges And ECC registers are in the DDR controllers? I would expect the DT to have 4 DDR controller nodes and probably 2 bridges. The memory bridges have control registers? > 2. 4 CPU's domain with one shared top level interrupt, shared L2 for > two CPU's, and individual L1 > 3. 1 L3 with one shared top level interrupt Presumably the registers for ECC are wired to some other block and not CPU registers? > 4. One SoC memory parity block with one shared top level interupt Shared interrupts are easily supported, but implicit in the DT. Otherwise, it seems this block is independent from the rest, correct? Rob -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
