Hi, >> > Similar comments for the rest. I would define memory controller >> > bindings and EDAC driver, then worry about the rest. >> >> Okay.. As comment in following emails, I will break up the driver into >> multiple drivers and focus only on the memory controller driver first. > > Please no multiple EDAC drivers. Or do you mean something else here? We will have the following: xgene-edac-mc.c xgene-edac-pmd.c xgene-edac-l3.c xgene-edac-soc.c Or what would you suggest. There are the following HW: 1. 4 DDR controller with one shared top level interrupt, two shared memory bridges 2. 4 CPU's domain with one shared top level interrupt, shared L2 for two CPU's, and individual L1 3. 1 L3 with one shared top level interrupt 4. One SoC memory parity block with one shared top level interupt -Loc -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
