The MT8188 SoC has three USB controllers, and all of them are behind
the MTU3 DRD controller.
Add the missing MTU3 nodes, default disabled, for all USB controllers
and move the related XHCI nodes to be children of their MTU3 DRD to
correctly describe the SoC.
In order to retain USB functionality on all of the MT8188 and MT8390
boards, also move the vusb33 supply and enable the relevant MTU3 nodes
with special attention to the MT8188 Geralt Chromebooks, where it was
necessary to set the dr_mode of all MTU3 controllers to host to avoid
interfering with the EC performing DRD on its own.
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@xxxxxxxxxxxxx>
---
.../boot/dts/mediatek/mt8188-geralt.dtsi | 18 +++
arch/arm64/boot/dts/mediatek/mt8188.dtsi | 121 ++++++++++++------
.../dts/mediatek/mt8390-genio-700-evk.dts | 28 ++++
3 files changed, 125 insertions(+), 42 deletions(-)
diff --git a/arch/arm64/boot/dts/mediatek/mt8188-geralt.dtsi b/arch/arm64/boot/dts/mediatek/mt8188-geralt.dtsi
index b6abecbcfa81..faed5c8bc721 100644
--- a/arch/arm64/boot/dts/mediatek/mt8188-geralt.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8188-geralt.dtsi
@@ -1103,6 +1103,12 @@ &u3phy2 {
};
/* USB detachable base */
+&ssusb0 {
+ dr_mode = "host";
+ vusb33-supply = <&pp3300_s3>;
+ status = "okay";
+};
+
&xhci0 {
/* controlled by EC */
vbus-supply = <&pp3300_z1>;
@@ -1110,6 +1116,12 @@ &xhci0 {
};
/* USB3 hub */
+&ssusb1 {
+ dr_mode = "host";
+ vusb33-supply = <&pp3300_s3>;
+ status = "okay";
+};
+
&xhci1 {
vusb33-supply = <&pp3300_s3>;
vbus-supply = <&pp5000_usb_vbus>;
@@ -1117,6 +1129,12 @@ &xhci1 {
};
/* USB BT */
+&ssusb2 {
+ dr_mode = "host";
+ vusb33-supply = <&pp3300_s3>;
+ status = "okay";
+};
+
&xhci2 {
/* no power supply since MT7921's power is controlled by PCIe */
/* MT7921's USB BT has issues with USB2 LPM */
diff --git a/arch/arm64/boot/dts/mediatek/mt8188.dtsi b/arch/arm64/boot/dts/mediatek/mt8188.dtsi
index f324d5f57789..ce676b0465d4 100644
--- a/arch/arm64/boot/dts/mediatek/mt8188.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8188.dtsi
@@ -1650,6 +1650,38 @@ spi5: spi@11019000 {
status = "disabled";
};
+ ssusb1: usb@11201000 {
+ compatible = "mediatek,mt8188-mtu3", "mediatek,mtu3";
+ reg = <0 0x11201000 0 0x2dff>, <0 0x11203e00 0 0x0100>;
+ reg-names = "mac", "ippc";
+ ranges = <0 0 0 0x11200000 0 0x3f00>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ interrupts-extended = <&gic GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH 0>;
+ assigned-clocks = <&topckgen CLK_TOP_USB_TOP>;
+ assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>;
+ clocks = <&pericfg_ao CLK_PERI_AO_SSUSB_BUS>,
+ <&topckgen CLK_TOP_SSUSB_TOP_REF>,
+ <&pericfg_ao CLK_PERI_AO_SSUSB_XHCI>;
+ clock-names = "sys_ck", "ref_ck", "mcu_ck";
+ phys = <&u2port1 PHY_TYPE_USB2>, <&u3port1 PHY_TYPE_USB3>;
+ wakeup-source;
+ mediatek,syscon-wakeup = <&pericfg 0x468 2>;
+ status = "disabled";
+
+ xhci1: usb@0 {
+ compatible = "mediatek,mt8188-xhci", "mediatek,mtk-xhci";
+ reg = <0 0 0 0x1000>;
+ reg-names = "mac";
+ interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH 0>;
+ assigned-clocks = <&topckgen CLK_TOP_SSUSB_XHCI>;
+ assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>;
+ clocks = <&pericfg_ao CLK_PERI_AO_SSUSB_XHCI>;
+ clock-names = "sys_ck";
+ status = "disabled";
+ };
+ };
+
eth: ethernet@11021000 {
compatible = "mediatek,mt8188-gmac", "mediatek,mt8195-gmac",
"snps,dwmac-5.10a";
@@ -1747,27 +1779,6 @@ queue3 {
};
};
- xhci1: usb@11200000 {
- compatible = "mediatek,mt8188-xhci", "mediatek,mtk-xhci";
- reg = <0 0x11200000 0 0x1000>,
- <0 0x11203e00 0 0x0100>;
- reg-names = "mac", "ippc";
- interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH 0>;
- phys = <&u2port1 PHY_TYPE_USB2>,
- <&u3port1 PHY_TYPE_USB3>;
- assigned-clocks = <&topckgen CLK_TOP_USB_TOP>,
- <&topckgen CLK_TOP_SSUSB_XHCI>;
- assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>,
- <&topckgen CLK_TOP_UNIVPLL_D5_D4>;
- clocks = <&pericfg_ao CLK_PERI_AO_SSUSB_BUS>,
- <&topckgen CLK_TOP_SSUSB_TOP_REF>,
- <&pericfg_ao CLK_PERI_AO_SSUSB_XHCI>;
- clock-names = "sys_ck", "ref_ck", "mcu_ck";
- mediatek,syscon-wakeup = <&pericfg 0x468 2>;
- wakeup-source;
- status = "disabled";
- };
-
mmc0: mmc@11230000 {
compatible = "mediatek,mt8188-mmc", "mediatek,mt8183-mmc";
reg = <0 0x11230000 0 0x10000>,
@@ -1868,42 +1879,68 @@ imp_iic_wrap_c: clock-controller@11283000 {
#clock-cells = <1>;
};
- xhci2: usb@112a0000 {
- compatible = "mediatek,mt8188-xhci", "mediatek,mtk-xhci";
- reg = <0 0x112a0000 0 0x1000>,
- <0 0x112a3e00 0 0x0100>;
+ ssusb2: usb@112a1000 {
+ compatible = "mediatek,mt8188-mtu3", "mediatek,mtu3";
+ reg = <0 0x112a1000 0 0x2dff>, <0 0x112a3e00 0 0x0100>;
reg-names = "mac", "ippc";
- interrupts = <GIC_SPI 536 IRQ_TYPE_LEVEL_HIGH 0>;
- phys = <&u2port2 PHY_TYPE_USB2>;
- assigned-clocks = <&topckgen CLK_TOP_SSUSB_XHCI_3P>,
- <&topckgen CLK_TOP_USB_TOP_3P>;
- assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>,
- <&topckgen CLK_TOP_UNIVPLL_D5_D4>;
+ ranges = <0 0 0 0x112a0000 0 0x3f00>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ interrupts-extended = <&gic GIC_SPI 535 IRQ_TYPE_LEVEL_HIGH 0>;
+ assigned-clocks = <&topckgen CLK_TOP_USB_TOP_3P>;
+ assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>;
clocks = <&pericfg_ao CLK_PERI_AO_SSUSB_3P_BUS>,
<&topckgen CLK_TOP_SSUSB_TOP_P3_REF>,
<&pericfg_ao CLK_PERI_AO_SSUSB_3P_XHCI>;
clock-names = "sys_ck", "ref_ck", "mcu_ck";
+ phys = <&u2port2 PHY_TYPE_USB2>;
+ wakeup-source;
+ mediatek,syscon-wakeup = <&pericfg 0x470 2>;
status = "disabled";
+
+ xhci2: usb@0 {
+ compatible = "mediatek,mt8188-xhci", "mediatek,mtk-xhci";
+ reg = <0 0 0 0x1000>;
+ reg-names = "mac";
+ interrupts = <GIC_SPI 536 IRQ_TYPE_LEVEL_HIGH 0>;
+ assigned-clocks = <&topckgen CLK_TOP_SSUSB_XHCI_3P>;
+ assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>;
+ clocks = <&pericfg_ao CLK_PERI_AO_SSUSB_3P_XHCI>;
+ clock-names = "sys_ck";
+ status = "disabled";
+ };
};
- xhci0: usb@112b0000 {
- compatible = "mediatek,mt8188-xhci", "mediatek,mtk-xhci";
- reg = <0 0x112b0000 0 0x1000>,
- <0 0x112b3e00 0 0x0100>;
+ ssusb0: usb@112b1000 {
+ compatible = "mediatek,mt8188-mtu3", "mediatek,mtu3";
+ reg = <0 0x112b1000 0 0x2dff>, <0 0x112b3e00 0 0x0100>;
reg-names = "mac", "ippc";
- interrupts = <GIC_SPI 533 IRQ_TYPE_LEVEL_HIGH 0>;
- phys = <&u2port0 PHY_TYPE_USB2>;
- assigned-clocks = <&topckgen CLK_TOP_SSUSB_XHCI_2P>,
- <&topckgen CLK_TOP_USB_TOP_2P>;
- assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>,
- <&topckgen CLK_TOP_UNIVPLL_D5_D4>;
+ ranges = <0 0 0 0x112b0000 0 0x3f00>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ interrupts-extended = <&gic GIC_SPI 532 IRQ_TYPE_LEVEL_HIGH 0>;
+ assigned-clocks = <&topckgen CLK_TOP_SSUSB_XHCI_2P>;
+ assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>;
clocks = <&pericfg_ao CLK_PERI_AO_SSUSB_2P_BUS>,
<&topckgen CLK_TOP_SSUSB_TOP_P2_REF>,
<&pericfg_ao CLK_PERI_AO_SSUSB_2P_XHCI>;
clock-names = "sys_ck", "ref_ck", "mcu_ck";
- mediatek,syscon-wakeup = <&pericfg 0x460 2>;
+ phys = <&u2port0 PHY_TYPE_USB2>;
wakeup-source;
+ mediatek,syscon-wakeup = <&pericfg 0x460 2>;
status = "disabled";
+
+ xhci0: usb@0 {
+ compatible = "mediatek,mt8188-xhci", "mediatek,mtk-xhci";
+ reg = <0 0 0 0x1000>;
+ reg-names = "mac";
+ interrupts = <GIC_SPI 533 IRQ_TYPE_LEVEL_HIGH 0>;
+ assigned-clocks = <&topckgen CLK_TOP_USB_TOP_2P>;
+ assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>;
+ clocks = <&pericfg_ao CLK_PERI_AO_SSUSB_2P_XHCI>;
+ clock-names = "sys_ck";
+ status = "disabled";
+ };
};
pcie: pcie@112f0000 {
diff --git a/arch/arm64/boot/dts/mediatek/mt8390-genio-700-evk.dts b/arch/arm64/boot/dts/mediatek/mt8390-genio-700-evk.dts
index 92eb09dc959b..d1a4bd428767 100644
--- a/arch/arm64/boot/dts/mediatek/mt8390-genio-700-evk.dts
+++ b/arch/arm64/boot/dts/mediatek/mt8390-genio-700-evk.dts
@@ -1300,13 +1300,25 @@ vdosys1_ep_ext: endpoint@1 {
};
};
+&ssusb0 {
+ dr_mode = "host";
+ vusb33-supply = <&mt6359_vusb_ldo_reg>;
+ status = "okay";
+};
+
&xhci0 {
status = "okay";
+};
+
+&ssusb1 {
+ dr_mode = "host";
vusb33-supply = <&mt6359_vusb_ldo_reg>;
+ status = "okay";
};
&xhci1 {
status = "okay";
+ vdd-supply = <&usb_hub_fixed_3v3>;
vusb33-supply = <&mt6359_vusb_ldo_reg>;
#address-cells = <1>;
#size-cells = <0>;
@@ -1326,6 +1338,22 @@ hub_3_0: hub@2 {
reset-gpios = <&pio 7 GPIO_ACTIVE_HIGH>;
vdd-supply = <&usb_hub_fixed_3v3>;
};
+
+ port {
+ xhci_ss_ep: endpoint {
+ remote-endpoint = <&typec_con_ss>;
+ };
+ };
+};
+
+&ssusb2 {
+ interrupts-extended = <&gic GIC_SPI 536 IRQ_TYPE_LEVEL_HIGH 0>,
+ <&pio 220 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "host", "wakeup";
+
+ dr_mode = "host";
+ vusb33-supply = <&mt6359_vusb_ldo_reg>;
+ status = "okay";
};
&xhci2 {
--
2.48.1
