Hi Boris, >> >> > Similar comments for the rest. I would define memory controller >> >> > bindings and EDAC driver, then worry about the rest. >> >> >> >> Okay.. As comment in following emails, I will break up the driver into >> >> multiple drivers and focus only on the memory controller driver first. >> > >> > Please no multiple EDAC drivers. Or do you mean something else here? >> >> We will have the following: >> >> xgene-edac-mc.c >> xgene-edac-pmd.c >> xgene-edac-l3.c >> xgene-edac-soc.c >> >> Or what would you suggest. > > xgene-edac.c > > This granularity is insane. On x86 we have single EDAC drivers for > multiple CPU families and platforms. > > You can start carving out stuff when this is absolutely needed, i.e. > when an IP block is in multiple hw incarnations. And even then I'd be > sceptical and would really want to know whether it is even worth it to > have an EDAC module for it. > > So let's be conservative please. For now, let me just deal with the DDR module. Rob, Did I answered all your questions regarding the EDAC DT binding for memory controller? I would like to get this sorted out before I post another version. -Loc -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
