On Thu, Feb 13, 2025 at 08:38:15AM +0100, Jiri Slaby wrote: > On 12. 02. 25, 16:09, Andy Shevchenko wrote: ... > > > + pending = uart_port_tx(port, c, > > > + !(tegra_utc_tx_readl(tup, TEGRA_UTC_FIFO_STATUS) & TEGRA_UTC_FIFO_FULL), > > > + tegra_utc_tx_writel(tup, c, TEGRA_UTC_DATA)); > > > > Make the last two to reside in temporary variables with self-explanatory names. > > Not sure what you mean here? They are needed to be evaluated (read/written) > in every loop. Ah, uart_port_tx() is a macro! -- With Best Regards, Andy Shevchenko
