On Fri, Feb 07, 2025 at 10:30:25PM +0100, J. Neuschäfer via B4 Relay wrote:
> From: "J. Neuschäfer" <j.ne@xxxxxxxxxx>
>
> fsl-spi.txt contains the bindings for the fsl,spi and fsl,espi
> contollers. Convert them to YAML.
>
> Signed-off-by: J. Neuschäfer <j.ne@xxxxxxxxxx>
> ---
>
> V2:
> - add missing end-of-document ("...") markers
> - add missing constraints to interrupts, fsl,espi-num-chipselects,
> fsl,csbef and fsl,csaft properties
> - remove unnecessary type from clock-frequency property
> - fix property order to comply with dts coding style
> ---
> .../devicetree/bindings/spi/fsl,espi.yaml | 64 +++++++++++++++++++
> Documentation/devicetree/bindings/spi/fsl,spi.yaml | 73 ++++++++++++++++++++++
> Documentation/devicetree/bindings/spi/fsl-spi.txt | 62 ------------------
> 3 files changed, 137 insertions(+), 62 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/spi/fsl,espi.yaml b/Documentation/devicetree/bindings/spi/fsl,espi.yaml
> new file mode 100644
> index 0000000000000000000000000000000000000000..c504b7957dde39086ef7d7a7550d6169cf5ec407
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/spi/fsl,espi.yaml
> @@ -0,0 +1,64 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/spi/fsl,espi.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Freescale eSPI (Enhanced Serial Peripheral Interface) controller
> +
> +maintainers:
> + - J. Neuschäfer <j.ne@xxxxxxxxxx>
> +
> +properties:
> + compatible:
> + const: fsl,mpc8536-espi
> +
> + reg:
> + maxItems: 1
> +
> + interrupts:
> + maxItems: 1
> +
> + fsl,espi-num-chipselects:
> + $ref: /schemas/types.yaml#/definitions/uint32
> + enum: [ 1, 4 ]
> + description: The number of the chipselect signals.
> +
> + fsl,csbef:
> + $ref: /schemas/types.yaml#/definitions/uint32
> + minimum: 0
> + maximum: 15
> + description: Chip select assertion time in bits before frame starts
> +
> + fsl,csaft:
> + $ref: /schemas/types.yaml#/definitions/uint32
> + minimum: 0
> + maximum: 15
> + description: Chip select negation time in bits after frame ends
> +
> +required:
> + - compatible
> + - reg
> + - interrupts
> + - fsl,espi-num-chipselects
> +
> +allOf:
> + - $ref: spi-controller.yaml#
> +
> +unevaluatedProperties: false
> +
> +examples:
> + - |
> + spi@110000 {
> + compatible = "fsl,mpc8536-espi";
> + reg = <0x110000 0x1000>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + interrupts = <53 0x2>;
Use predefine's irq type macro.
> + interrupt-parent = <&mpic>;
> + fsl,espi-num-chipselects = <4>;
> + fsl,csbef = <1>;
> + fsl,csaft = <1>;
> + };
> +
> +...
> diff --git a/Documentation/devicetree/bindings/spi/fsl,spi.yaml b/Documentation/devicetree/bindings/spi/fsl,spi.yaml
> new file mode 100644
> index 0000000000000000000000000000000000000000..db65c0560c32f32324a2aaaf53c0044a4b56f3d9
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/spi/fsl,spi.yaml
> @@ -0,0 +1,73 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/spi/fsl,spi.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Freescale SPI (Serial Peripheral Interface) controller
> +
> +maintainers:
> + - J. Neuschäfer <j.ne@xxxxxxxxxx>
> +
> +properties:
> + compatible:
> + enum:
> + - fsl,spi
> + - aeroflexgaisler,spictrl
> +
> + reg:
> + maxItems: 1
> +
> + cell-index:
> + $ref: /schemas/types.yaml#/definitions/uint32
> + description: |
> + QE SPI subblock index.
> + 0: QE subblock SPI1
> + 1: QE subblock SPI2
> +
> + mode:
> + description: SPI operation mode
> + enum:
> + - cpu
> + - cpu-qe
> +
> + interrupts:
> + maxItems: 1
> +
> + clock-frequency:
> + description: input clock frequency to non FSL_SOC cores
> +
> + cs-gpios: true
> +
> + fsl,spisel_boot:
> + $ref: /schemas/types.yaml#/definitions/flag
> + description:
> + For the MPC8306 and MPC8309, specifies that the SPISEL_BOOT signal is used
> + as chip select for a slave device. Use reg = <number of gpios> in the
> + corresponding child node, i.e. 0 if the cs-gpios property is not present.
> +
> +required:
> + - compatible
> + - reg
> + - mode
> + - interrupts
> +
> +allOf:
> + - $ref: spi-controller.yaml#
> +
> +unevaluatedProperties: false
> +
> +examples:
> + - |
> + spi@4c0 {
> + compatible = "fsl,spi";
> + reg = <0x4c0 0x40>;
> + cell-index = <0>;
> + interrupts = <82 0>;
> + interrupt-parent = <&intc>;
> + mode = "cpu";
> + cs-gpios = <&gpio 18 1 // device reg=<0>
> + &gpio 19 1>; // device reg=<1>
use predefine gpio level macro
Frank
> + };
> +
> +...
> diff --git a/Documentation/devicetree/bindings/spi/fsl-spi.txt b/Documentation/devicetree/bindings/spi/fsl-spi.txt
> deleted file mode 100644
> index 0654380eb7515d8bda80eea1486e77b939ac38d8..0000000000000000000000000000000000000000
> --- a/Documentation/devicetree/bindings/spi/fsl-spi.txt
> +++ /dev/null
> @@ -1,62 +0,0 @@
> -* SPI (Serial Peripheral Interface)
> -
> -Required properties:
> -- cell-index : QE SPI subblock index.
> - 0: QE subblock SPI1
> - 1: QE subblock SPI2
> -- compatible : should be "fsl,spi" or "aeroflexgaisler,spictrl".
> -- mode : the SPI operation mode, it can be "cpu" or "cpu-qe".
> -- reg : Offset and length of the register set for the device
> -- interrupts : <a b> where a is the interrupt number and b is a
> - field that represents an encoding of the sense and level
> - information for the interrupt. This should be encoded based on
> - the information in section 2) depending on the type of interrupt
> - controller you have.
> -- clock-frequency : input clock frequency to non FSL_SOC cores
> -
> -Optional properties:
> -- cs-gpios : specifies the gpio pins to be used for chipselects.
> - The gpios will be referred to as reg = <index> in the SPI child nodes.
> - If unspecified, a single SPI device without a chip select can be used.
> -- fsl,spisel_boot : for the MPC8306 and MPC8309, specifies that the
> - SPISEL_BOOT signal is used as chip select for a slave device. Use
> - reg = <number of gpios> in the corresponding child node, i.e. 0 if
> - the cs-gpios property is not present.
> -
> -Example:
> - spi@4c0 {
> - cell-index = <0>;
> - compatible = "fsl,spi";
> - reg = <4c0 40>;
> - interrupts = <82 0>;
> - interrupt-parent = <700>;
> - mode = "cpu";
> - cs-gpios = <&gpio 18 1 // device reg=<0>
> - &gpio 19 1>; // device reg=<1>
> - };
> -
> -
> -* eSPI (Enhanced Serial Peripheral Interface)
> -
> -Required properties:
> -- compatible : should be "fsl,mpc8536-espi".
> -- reg : Offset and length of the register set for the device.
> -- interrupts : should contain eSPI interrupt, the device has one interrupt.
> -- fsl,espi-num-chipselects : the number of the chipselect signals.
> -
> -Optional properties:
> -- fsl,csbef: chip select assertion time in bits before frame starts
> -- fsl,csaft: chip select negation time in bits after frame ends
> -
> -Example:
> - spi@110000 {
> - #address-cells = <1>;
> - #size-cells = <0>;
> - compatible = "fsl,mpc8536-espi";
> - reg = <0x110000 0x1000>;
> - interrupts = <53 0x2>;
> - interrupt-parent = <&mpic>;
> - fsl,espi-num-chipselects = <4>;
> - fsl,csbef = <1>;
> - fsl,csaft = <1>;
> - };
>
> --
> 2.48.0.rc1.219.gb6b6757d772
>
>
