Hi,
On 10/02/2025 12:15, Nitin Rawat wrote:
On 2/10/2025 3:09 PM, neil.armstrong@xxxxxxxxxx wrote:
On 09/02/2025 16:21, Manivannan Sadhasivam wrote:
On Fri, Feb 07, 2025 at 11:47:12PM +0100, Konrad Dybcio wrote:
On 13.01.2025 10:46 PM, Melody Olvera wrote:
Add UFS support for SM8750 SoCs.
Signed-off-by: Melody Olvera <quic_molvera@xxxxxxxxxxx>
---
Nitin Rawat (5):
dt-bindings: phy: qcom,sc8280xp-qmp-ufs-phy: Document the SM8750 QMP UFS PHY
phy: qcom-qmp-ufs: Add PHY Configuration support for SM8750
dt-bindings: ufs: qcom: Document the SM8750 UFS Controller
arm64: dts: qcom: sm8750: Add UFS nodes for SM8750 SoC
arm64: dts: qcom: sm8750: Add UFS nodes for SM8750 QRD and MTP boards
You still need the same workaround 8550/8650 have in the UFS driver
(UFSHCD_QUIRK_BROKEN_LSDBS_CAP) for it to work reliably, or at least
that was the case for me on a 8750 QRD.
Please check whether we can make that quirk apply based on ctrl
version or so, so that we don't have to keep growing the compatible
list in the driver.
That would be a bizarre. When I added the quirk, I was told that it would affect
only SM8550 and SM8650 (this one I learned later). I'm not against applying the
quirk based on UFSHC version if the bug is carried forward, but that would be an
indication of bad design.
Isn't 8750 capable of using MCQ now ? because this is the whole issue behind
this UFSHCD_QUIRK_BROKEN_LSDBS_CAP, it's supposed to use MCQ by default... but
we don't.
Is there any news about that ? It's a clear regression against downstream, not
having MCQ makes the UFS driver struggle to reach high bandwidth when the system
is busy because we can't spread the load over all CPUs and we have only single
queue to submit requests.
Hi Neil,
There is no relation b/w LSDBS_CAP Register and MCQ support.
That registers just indicate when MCQ support is present on any SOC,
whether Single queue mode is supported or not on that SOC.
In SM8650 and SM86550, just the pored value of that register was incorrect which was fixed by WA but actually functionality was present and working fine.
Pored value of that register has been fixed from SM8750 onwards.
Thanks for the explanation, but this doesn't answer about the state of MCQ
for SM8550, SM8650 and SM8750. I would've expected to have MCQ for SM8750
in the first patchset.
Neil
Regards,
Nitin
Neil
- Mani
