On Sun, Feb 09, 2025 at 11:06:28PM +0100, Alexander Sverdlin wrote:
> Add initial device tree for the SG2000 SoC by SOPHGO (from ARM64 PoV).
>
> Signed-off-by: Alexander Sverdlin <alexander.sverdlin@xxxxxxxxx>
Can you add a riscv version of the this file too? This also applies
to patch 4 and 5
Regards,
Inochi
> ---
> arch/arm64/boot/dts/sophgo/sg2000.dtsi | 79 ++++++++++++++++++++++++++
> 1 file changed, 79 insertions(+)
> create mode 100644 arch/arm64/boot/dts/sophgo/sg2000.dtsi
>
> diff --git a/arch/arm64/boot/dts/sophgo/sg2000.dtsi b/arch/arm64/boot/dts/sophgo/sg2000.dtsi
> new file mode 100644
> index 000000000000..4e520486cbe5
> --- /dev/null
> +++ b/arch/arm64/boot/dts/sophgo/sg2000.dtsi
> @@ -0,0 +1,79 @@
> +// SPDX-License-Identifier: (GPL-2.0 OR MIT)
> +
> +#define SOC_PERIPHERAL_IRQ(nr) GIC_SPI (nr)
> +
> +#include <dt-bindings/interrupt-controller/arm-gic.h>
> +#include <riscv/sophgo/cv18xx-periph.dtsi>
> +#include <riscv/sophgo/cv181x.dtsi>
> +
> +/ {
> + #address-cells = <1>;
> + #size-cells = <1>;
> + compatible = "sophgo,sg2000";
> + interrupt-parent = <&gic>;
> +
> + memory@80000000 {
> + device_type = "memory";
> + reg = <0x80000000 0x20000000>; /* 512MiB */
> + };
> +
> + cpus {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + cpu@0 {
> + compatible = "arm,cortex-a53";
> + device_type = "cpu";
> + reg = <0>;
> + i-cache-size = <32768>;
> + d-cache-size = <32768>;
> + next-level-cache = <&l2>;
> + };
> +
> + l2: l2-cache {
> + compatible = "cache";
> + cache-level= <2>;
> + cache-size = <0x20000>;
> + };
> + };
> +
> + pmu {
> + compatible = "arm,cortex-a53-pmu";
> + interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
> + };
> +
> + timer {
> + compatible = "arm,armv8-timer";
> + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
> + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
> + <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
> + <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
> + always-on;
> + clock-frequency = <25000000>;
> + };
> +
> + gic: interrupt-controller@1f01000 {
> + compatible = "arm,cortex-a15-gic";
> + interrupt-controller;
> + #interrupt-cells = <3>;
> + reg = <0x01f01000 0x1000>,
> + <0x01f02000 0x2000>;
> + };
> +
> + soc {
> + ranges;
> +
> + pinctrl: pinctrl@3001000 {
> + compatible = "sophgo,sg2000-pinctrl";
> + reg = <0x03001000 0x1000>,
> + <0x05027000 0x1000>;
> + reg-names = "sys", "rtc";
> + };
> + };
> +};
> +
> +
> +&clk {
> + compatible = "sophgo,sg2000-clk";
> +};
> --
> 2.48.1
>
