These definitions define the location of corresponding disable bits in OCOTP peripheral. Signed-off-by: Alexander Stein <alexander.stein@xxxxxxxxxxxxxxx> --- arch/arm64/boot/dts/freescale/imx8mn-ocotp.h | 26 ++++++++++++++++++++ 1 file changed, 26 insertions(+) create mode 100644 arch/arm64/boot/dts/freescale/imx8mn-ocotp.h diff --git a/arch/arm64/boot/dts/freescale/imx8mn-ocotp.h b/arch/arm64/boot/dts/freescale/imx8mn-ocotp.h new file mode 100644 index 0000000000000..43583c4a70156 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mn-ocotp.h @@ -0,0 +1,26 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) +/* + * Copyright (c) 2025 TQ-Systems GmbH <linux@xxxxxxxxxxxxxxx>, + * D-82229 Seefeld, Germany. + * Author: Alexander Stein + */ + +#ifndef __DTS_IMX8MN_OCOTP_H +#define __DTS_IMX8MN_OCOTP_H + +/* + * The OCOTP is a tuple of + * <fuse_addr fuse_bit_offset> + */ + +#define IMX8MN_OCOTP_M7_DISABLE 20 8 +#define IMX8MN_OCOTP_M7_MPU_DISABLE 20 9 +#define IMX8MN_OCOTP_M7_FPU_DISABLE 20 10 +#define IMX8MN_OCOTP_USB_OTG1_DISABLE 20 11 +#define IMX8MN_OCOTP_GPU3D_DISABLE 20 24 +#define IMX8MN_OCOTP_MIPI_DSI_DISABLE 20 28 +#define IMX8MN_OCOTP_ENET_DISABLE 20 29 +#define IMX8MN_OCOTP_MIPI_CSI_DISABLE 20 30 +#define IMX8MN_OCOTP_ASRC_DISABLE 20 31 + +#endif /* __DTS_IMX8MN_OCOTP_H */ -- 2.34.1
