i.MX8M OCOTP supports a specific peripheral or function being fused
which means disabled, so
- Introduce disable_fuse for a list of possible fused peripherals.
- Iterate all nodes to check accessing permission. If not
allowed to be accessed, detach the node
Signed-off-by: Alexander Stein <alexander.stein@xxxxxxxxxxxxxxx>
---
drivers/nvmem/Kconfig | 3 ++
drivers/nvmem/imx-ocotp.c | 74 ++++++++++++++++++++++++++++++++++++++-
2 files changed, 76 insertions(+), 1 deletion(-)
diff --git a/drivers/nvmem/Kconfig b/drivers/nvmem/Kconfig
index 8671b7c974b93..ba5c928cab520 100644
--- a/drivers/nvmem/Kconfig
+++ b/drivers/nvmem/Kconfig
@@ -84,6 +84,9 @@ config NVMEM_IMX_OCOTP
This driver can also be built as a module. If so, the module
will be called nvmem-imx-ocotp.
+ If built as modules, any other driver relying on this working
+ as access controller also needs to be a module as well.
+
config NVMEM_IMX_OCOTP_ELE
tristate "i.MX On-Chip OTP Controller support"
depends on ARCH_MXC || COMPILE_TEST
diff --git a/drivers/nvmem/imx-ocotp.c b/drivers/nvmem/imx-ocotp.c
index c5086a16450ac..b15cbdae66a7c 100644
--- a/drivers/nvmem/imx-ocotp.c
+++ b/drivers/nvmem/imx-ocotp.c
@@ -589,6 +589,74 @@ static void imx_ocotp_fixup_dt_cell_info(struct nvmem_device *nvmem,
cell->read_post_process = imx_ocotp_cell_pp;
}
+static int imx_ocotp_check_access(struct ocotp_priv *priv, u32 addr, u32 bit)
+{
+ u32 mask, ret, val;
+
+ mask = BIT(bit);
+
+ ret = imx_ocotp_read(priv, addr, &val, sizeof(val));
+ if (ret)
+ return ret;
+
+ /* true means disabled */
+ if (val & mask)
+ return -EACCES;
+
+ return 0;
+}
+
+static int imx_ocotp_grant_access(struct ocotp_priv *priv, struct device_node *parent)
+{
+ struct device *dev = priv->dev;
+
+ for_each_available_child_of_node_scoped(parent, child) {
+ struct of_phandle_args args;
+ u32 idx = 0;
+ u32 addr;
+ u32 bit;
+
+ while (!of_parse_phandle_with_args(child, "access-controllers",
+ "#access-controller-cells",
+ idx++, &args)) {
+ of_node_put(args.np);
+ if (args.np != dev->of_node)
+ continue;
+
+ /* Only support one cell */
+ if (args.args_count != 2) {
+ dev_err(dev, "wrong args count\n");
+ continue;
+ }
+
+ addr = args.args[0];
+ bit = args.args[1];
+
+ dev_dbg(dev, "Checking node: %pOF disable fuse addr: %u, bit %u\n", child, addr, bit);
+
+ if (imx_ocotp_check_access(priv, addr, bit)) {
+ of_detach_node(child);
+ dev_info(dev, "%pOF: disabled by fuse, device driver will not be probed\n",
+ child);
+ }
+ }
+
+ imx_ocotp_grant_access(priv, child);
+ }
+
+ return 0;
+}
+
+static int imx_ocotp_access_control(struct ocotp_priv *priv)
+{
+ struct device_node *root __free(device_node) = of_find_node_by_path("/");
+
+ if (WARN_ON(!root))
+ return -EINVAL;
+
+ return imx_ocotp_grant_access(priv, root);
+}
+
static int imx_ocotp_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
@@ -622,9 +690,13 @@ static int imx_ocotp_probe(struct platform_device *pdev)
imx_ocotp_clr_err_if_set(priv);
clk_disable_unprepare(priv->clk);
+ platform_set_drvdata(pdev, priv);
+
nvmem = devm_nvmem_register(dev, &imx_ocotp_nvmem_config);
+ if (IS_ERR(nvmem))
+ return PTR_ERR(nvmem);
- return PTR_ERR_OR_ZERO(nvmem);
+ return imx_ocotp_access_control(priv);
}
static struct platform_driver imx_ocotp_driver = {
--
2.34.1
