On Thu, 30 Jan 2025, Krzysztof Kozlowski wrote:
On 29/01/2025 20:42, matthew.gerlach@xxxxxxxxxxxxxxx wrote:
On Wed, 29 Jan 2025, Krzysztof Kozlowski wrote:
On 27/01/2025 18:35, Matthew Gerlach wrote:
Add the base device tree for support of the PCIe Root Port
for the Agilex family of chips.
Signed-off-by: Matthew Gerlach <matthew.gerlach@xxxxxxxxxxxxxxx>
---
v3:
- Remove accepted patches from patch set.
v2:
- Rename node to fix schema check error.
---
.../intel/socfpga_agilex_pcie_root_port.dtsi | 55 +++++++++++++++++++
1 file changed, 55 insertions(+)
create mode 100644 arch/arm64/boot/dts/intel/socfpga_agilex_pcie_root_port.dtsi
diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex_pcie_root_port.dtsi b/arch/arm64/boot/dts/intel/socfpga_agilex_pcie_root_port.dtsi
new file mode 100644
index 000000000000..50f131f5791b
--- /dev/null
+++ b/arch/arm64/boot/dts/intel/socfpga_agilex_pcie_root_port.dtsi
@@ -0,0 +1,55 @@
+// SPDX-License-Identifier: GPL-2.0
Odd spaces in SPDX tag.
Yes, there should only be one space.
+/*
+ * Copyright (C) 2024, Intel Corporation
+ */
+&soc0 {
+ aglx_hps_bridges: fpga-bus@80000000 {
+ compatible = "simple-bus";
+ reg = <0x80000000 0x20200000>,
+ <0xf9000000 0x00100000>;
+ reg-names = "axi_h2f", "axi_h2f_lw";
Where is this binding defined?
The bindings for these reg-names are not currently defined anywhere, but
Then you cannot use them.
they are also referenced in the following:
Documentation/devicetree/bindings/soc/intel/intel,hps-copy-engine.yaml
arch/arm64/boot/dts/intel/socfpga_agilex_n6000.dts
I am not exactly sure where the right place is to define them, maybe
Documentation/devicetree/bindings/arm/intel,socfpga.yaml. On the other
hand, no code references these names; so it might make sense to just
remove them.
In general: nowhere, because simple bus does not have such properties.
It's not about reg-names only - you cannot have reg. You just did not
define here simple-bus.
I understand. I will remove reg and reg-names.
Best regards,
Krzysztof
Thanks for the review,
Matthew Gerlach
