On Wed, 29 Jan 2025, Krzysztof Kozlowski wrote:
On 27/01/2025 18:35, Matthew Gerlach wrote:
Add the base device tree for support of the PCIe Root Port
for the Agilex family of chips.
Signed-off-by: Matthew Gerlach <matthew.gerlach@xxxxxxxxxxxxxxx>
---
v3:
- Remove accepted patches from patch set.
v2:
- Rename node to fix schema check error.
---
.../intel/socfpga_agilex_pcie_root_port.dtsi | 55 +++++++++++++++++++
1 file changed, 55 insertions(+)
create mode 100644 arch/arm64/boot/dts/intel/socfpga_agilex_pcie_root_port.dtsi
diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex_pcie_root_port.dtsi b/arch/arm64/boot/dts/intel/socfpga_agilex_pcie_root_port.dtsi
new file mode 100644
index 000000000000..50f131f5791b
--- /dev/null
+++ b/arch/arm64/boot/dts/intel/socfpga_agilex_pcie_root_port.dtsi
@@ -0,0 +1,55 @@
+// SPDX-License-Identifier: GPL-2.0
Odd spaces in SPDX tag.
Yes, there should only be one space.
+/*
+ * Copyright (C) 2024, Intel Corporation
+ */
+&soc0 {
+ aglx_hps_bridges: fpga-bus@80000000 {
+ compatible = "simple-bus";
+ reg = <0x80000000 0x20200000>,
+ <0xf9000000 0x00100000>;
+ reg-names = "axi_h2f", "axi_h2f_lw";
Where is this binding defined?
The bindings for these reg-names are not currently defined anywhere, but
they are also referenced in the following:
Documentation/devicetree/bindings/soc/intel/intel,hps-copy-engine.yaml
arch/arm64/boot/dts/intel/socfpga_agilex_n6000.dts
I am not exactly sure where the right place is to define them, maybe
Documentation/devicetree/bindings/arm/intel,socfpga.yaml. On the other
hand, no code references these names; so it might make sense to just
remove them.
+ #address-cells = <0x2>;
+ #size-cells = <0x1>;
These two are not hex.
I will change all #address-cells and #size-cell to decimal.
+ ranges = <0x00000000 0x00000000 0x80000000 0x00040000>,
+ <0x00000000 0x10000000 0x90100000 0x0ff00000>,
+ <0x00000000 0x20000000 0xa0000000 0x00200000>,
+ <0x00000001 0x00010000 0xf9010000 0x00008000>,
+ <0x00000001 0x00018000 0xf9018000 0x00000080>,
+ <0x00000001 0x00018080 0xf9018080 0x00000010>;
+
+ pcie_0_pcie_aglx: pcie@200000000 {
+ reg = <0x00000000 0x10000000 0x10000000>,
+ <0x00000001 0x00010000 0x00008000>,
+ <0x00000000 0x20000000 0x00200000>;
+ reg-names = "Txs", "Cra", "Hip";
Where is this binding defined?
Documentation/devicetree/bindings/pci/altr,pcie-root-port.yaml
+ interrupt-parent = <&intc>;
+ interrupts = <GIC_SPI 0x14 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-controller;
+ #interrupt-cells = <0x1>;
+ device_type = "pci";
+ bus-range = <0x0000000 0x000000ff>;
+ ranges = <0x82000000 0x00000000 0x00100000 0x00000000 0x10000000 0x00000000 0x0ff00000>;
+ msi-parent = <&pcie_0_msi_irq>;
+ #address-cells = <0x3>;
+ #size-cells = <0x2>;
Same problem for all cells.
+ interrupt-map-mask = <0x0 0x0 0x0 0x7>;
+ interrupt-map = <0x0 0x0 0x0 0x1 &pcie_0_pcie_aglx 0 0 0 0x1>,
+ <0x0 0x0 0x0 0x2 &pcie_0_pcie_aglx 0 0 0 0x2>,
+ <0x0 0x0 0x0 0x3 &pcie_0_pcie_aglx 0 0 0 0x3>,
+ <0x0 0x0 0x0 0x4 &pcie_0_pcie_aglx 0 0 0 0x4>;
+ status = "disabled";
+ };
+
+ pcie_0_msi_irq: msi@10008080 {
+ compatible = "altr,msi-1.0";
+ reg = <0x00000001 0x00018080 0x00000010>,
+ <0x00000001 0x00018000 0x00000080>;
+ reg-names = "csr", "vector_slave";
+ interrupt-parent = <&intc>;
+ interrupts = <GIC_SPI 0x13 IRQ_TYPE_LEVEL_HIGH>;
+ msi-controller;
+ num-vectors = <0x20>;
That's decimal. Value is for humans and we count numbers in decimal.
I will change num-vectors to decimal.
Thanks for the review,
Matthew Gerlach
Best regards,
Krzysztof
