On Fri, Jan 31, 2025 at 05:19:09PM +0530, Alim Akhtar wrote: > Hi Devang > > > > > Add CPU caches information to its dt nodes so that the same is available to > > userspace via sysfs. This SoC has 64/64 KB I/D cache and 256KB of L2 cache for > > each core, 2 MB of shared L3 cache for each quad cpu cluster and 1 MB of > > shared L3 cache for the dual cpu cluster. > > > > Signed-off-by: Devang Tailor <dev.tailor@xxxxxxxxxxx> > > > > --- > > Changes in v2: > > - Added L3 cache for all the three cpu clusters > > - Corrected L2 cache numbering as a part of review comments from Krzysztof > > and updated as per cpus clusters. > > - Link to v1: https://patchwork.kernel.org/project/linux-arm- > > kernel/patch/20241231064350.523713-1-dev.tailor@xxxxxxxxxxx/ > > --- > > .../arm64/boot/dts/exynos/exynosautov920.dtsi | 127 > > ++++++++++++++++++ > > 1 file changed, 127 insertions(+) > > > [snip] > > + l3_cache_cl0: l3-cache0 { > You can add one node for cl0 and cl1, say "l3_cache_cl0_cl1" and > Remove the specific node for CL1, because both are same. > What do you mean by "both are same" ? Do you mean both have exact same properties but are physically different caches ? OR Do you mean it is just one shared cache ? If former, we still need distinct node to get the cacheinfo about shareability correct. If this is about avoiding duplication of errors, you can probably define some macro and avoid it, but we need 2 nodes in the devicetree. If latter, you suggestion is correct. -- Regards, Sudeep
