Hi, On 1/28/25 7:55 PM, Florian Fainelli wrote: > On 1/27/25 10:10, Thomas Gleixner wrote: >> On Mon, Jan 20 2025 at 15:01, Stanimir Varbanov wrote: >> >>> Add an interrupt controller driver for MSI-X Interrupt Peripheral (MIP) >>> hardware block found in bcm2712. The interrupt controller is used to >>> handle MSI-X interrupts from peripherials behind PCIe endpoints like >>> RP1 south bridge found in RPi5. >>> >>> There are two MIPs on bcm2712, the first has 64 consecutive SPIs >>> assigned to 64 output vectors, and the second has 17 SPIs, but only >>> 8 of them are consecutive starting at the 8th output vector. >>> >>> Signed-off-by: Stanimir Varbanov <svarbanov@xxxxxxx> >> >> Reviewed-by: Thomas Gleixner <tglx@xxxxxxxxxxxxx> >> >> As this is a new controller and required for the actual PCI muck, I >> think the best way is to take it through the PCI tree, unless someone >> wants me to pick the whole lot up. > > Agreed, the PCI maintainers should take patches 1 through 9 inclusive, Just small correction, patch 09/11 [1] has a new v2 at [2]. And I think PCI maintainer have to take v2. > and I will take patches 10-11 through the Broadcom ARM SoC tree, Bjorn, > KW, does that work? ~Stan [1] [PATCH v5 -next 09/11] PCI: brcmstb: Fix for missing of_node_put [2] https://lore.kernel.org/lkml/20250122222955.1752778-1-svarbanov@xxxxxxx/T/
