The Tegra UTC (UART Trace Controller) is a HW based serial port that allows multiplexing multiple data streams of up to 16 UTC clients into a single hardware serial port. Add bindings for the Tegra UTC client device. Signed-off-by: Kartik Rajput <kkartik@xxxxxxxxxx> --- .../bindings/serial/nvidia,tegra264-utc.yaml | 83 +++++++++++++++++++ 1 file changed, 83 insertions(+) create mode 100644 Documentation/devicetree/bindings/serial/nvidia,tegra264-utc.yaml diff --git a/Documentation/devicetree/bindings/serial/nvidia,tegra264-utc.yaml b/Documentation/devicetree/bindings/serial/nvidia,tegra264-utc.yaml new file mode 100644 index 000000000000..63ba3655451f --- /dev/null +++ b/Documentation/devicetree/bindings/serial/nvidia,tegra264-utc.yaml @@ -0,0 +1,83 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/serial/nvidia,tegra264-utc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NVIDIA Tegra UART Trace Controller (UTC) client + +maintainers: + - Kartik Rajput <kkartik@xxxxxxxxxx> + - Thierry Reding <thierry.reding@xxxxxxxxx> + - Jonathan Hunter <jonathanh@xxxxxxxxxx> + +description: + The Tegra UTC (UART Trace Controller) is a hardware controller that + allows multiple systems within the Tegra SoC to share a hardware UART + interface. It supports up to 16 clients, with each client having its own + interrupt and a FIFO buffer for both RX (receive) and TX (transmit), each + capable of holding 128 characters. + + The Tegra UTC uses 8-N-1 configuration and operates on a pre-configured + baudrate, which is configured by the bootloader. + +properties: + $nodename: + pattern: "^serial(@.*)?$" + + compatible: + const: nvidia,tegra264-utc + + reg: + items: + - description: Register region for TX client. + - description: Register region for RX client. + minItems: 2 + + reg-names: + items: + - const: tx + - const: rx + minItems: 2 + + interrupts: + maxItems: 1 + + current-speed: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + This property specifies the baudrate at which the Tegra UTC is + operating. + + nvidia,utc-fifo-threshold: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + This property specifies the UTC TX and RX client FIFO threshold in + terms of occupancy. + + This property should have the same value as the burst size (number + of characters read by the Tegra UTC hardware at a time from each + client) which is configured by the bootloader. + +required: + - compatible + - reg + - reg-names + - interrupts + - current-speed + - nvidia,utc-fifo-threshold + +additionalProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + + tegra_utc: serial@c4e0000 { + compatible = "nvidia,tegra264-utc"; + reg = <0xc4e0000 0x8000>, <0xc4e8000 0x8000>; + reg-names = "tx", "rx"; + interrupts = <GIC_SPI 514 IRQ_TYPE_LEVEL_HIGH>; + current-speed = <115200>; + nvidia,utc-fifo-threshold = <4>; + }; -- 2.43.0
